公开(公告)号：US10684123B2

公开(公告)日：2020-06-16

申请号：US15872163

申请日：2018-01-16

Applicant: CISCO TECHNOLOGY, INC.

Inventor： Amendra Koul ,  Yaochao Yang ,  Mike Sapozhnikov ,  Joel Richard Goergen ,  Kartheek Nalla

IPC: G01B11/04 ,  G01B11/24 ,  G01N21/956 ,  G01B11/26 ,  H05K3/00

Abstract: In one embodiment, a method generally comprises importing a layout identifying routing information for a plurality of differential pair traces on a printed circuit board at a skew assessment module, receiving values for a plurality of skew parameters associated with fiber weave skew, receiving variation parameters from a database comprising data collected on fiber weave variation for one or more of the skew parameters, calculating a skew estimate for the printed circuit board based on the skew parameters and the variation parameters at the skew assessment module, and determining if the skew estimate is within a specified skew allowance for the printed circuit board.

公开(公告)号：US20250133652A1

公开(公告)日：2025-04-24

申请号：US18532182

申请日：2023-12-07

Applicant: Cisco Technology, Inc.

Inventor： Yuqing Zhu ,  Wenbin Ma ,  Mike Sapozhnikov ,  Weiying Ding ,  Mingjian Gao ,  Mingtong Zuo ,  David Nozadze ,  Joel Richard Goergen

IPC: H05K1/02 ,  H01L21/48 ,  H01L23/498 ,  H05K3/40

Abstract: In some embodiments, an apparatus includes a layer of a printed circuit board (PCB), a pair of signal vias formed on the layer of the PCB and including a first signal via a second signal via each configured to propagate a respective signal, a first plurality of ground vias formed on the layer and at least partially circumferentially surrounding the first signal via of the pair of signal vias, and a second plurality of ground vias formed on the layer and at least partially circumferentially surrounding the second signal via of the pair of signal vias. The first plurality of ground vias and the second plurality of ground vias include a shared ground via.

公开(公告)号：US12142578B2

公开(公告)日：2024-11-12

申请号：US17492836

申请日：2021-10-04

Applicant: Cisco Technology, Inc.

Inventor： Xiaohong Wu ,  Xing Wang ,  Mike Sapozhnikov ,  Sayed Ashraf Mamun ,  Tomer Osi ,  Joel Goergen

IPC: H01L23/50 ,  H01L23/00 ,  H01L23/053 ,  H01R12/00 ,  H05K1/18 ,  H05K7/10

Abstract: An apparatus includes a printed circuit board (PCB), and an integrated circuit (IC) package connected with the PCB. The IC package includes a package substrate, a die secured to the package substrate and including an integrated circuit, and a stiffener ring secured to the package substrate and surrounding so as to define a perimeter around the die. The stiffener ring increases a rigidity of the package substrate and delivers electrical power to the integrated circuit, where the stiffener ring includes a first conductive layer forming a power (PWR) plane for the integrated circuit, a second conductive layer forming a ground (GND) plane for the integrated circuit, and an insulating layer disposed between the first conductive layer and the second conductive layer.

公开(公告)号：US20240355737A1

公开(公告)日：2024-10-24

申请号：US18304001

申请日：2023-04-20

Applicant: Cisco Technology, Inc.

Inventor： Wenbin Ma ,  Mike Sapozhnikov ,  Weiying Ding ,  David Nozadze ,  Yinxin Yang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L23/481

Abstract: In some aspects, the techniques described herein relate to an apparatus including: a semiconductor device substrate material; a first signal conductor incorporated into the semiconductor device substrate material; a second signal conductor incorporated into the semiconductor device substrate material; and a ground conductor incorporated into the semiconductor device substrate material between the first signal conductor and the second signal conductor, wherein the ground conductor includes a first elongated portion and a second elongated portion arranged at an angle relative to the first elongated portion.

公开(公告)号：US20240345180A1

公开(公告)日：2024-10-17

申请号：US18422854

申请日：2024-01-25

Applicant: Cisco Technology, Inc.

Inventor： David Nozadze ,  Mike Sapozhnikov ,  Upen Reddy Kareti ,  Amendra Koul ,  Joel Richard Goergen

IPC: G01R31/58 ,  G01R23/02

CPC classification number: G01R31/58 ,  G01R23/02

Abstract: Presented herein is a method comprising: determining skew values of cables, each skew value indicating a time of signal propagation along a respective cable at a respective signal frequency value, and the skew values being frequency dependent and varying at signal frequency values; determining skew behavior property values for each cable based on the skew values; determining a performance metric value for each skew behavior property value; determining a relationship between the skew values and the signal frequency values at each performance metric value based on the performance metric value for each skew behavior property value; and coupling a first electronic component and a second electronic component to one another using a new cable based on the relationship between the skew values and the signal frequency values at each performance metric value.

公开(公告)号：US20230397343A1

公开(公告)日：2023-12-07

申请号：US17942711

申请日：2022-09-12

Applicant: Cisco Technology, Inc.

Inventor： Mike Sapozhnikov ,  Sayed Ashraf Mamun ,  D. Brice Achkir ,  David Nozadze ,  Amendra Koul ,  Upen Reddy Kareti

IPC: H05K3/46 ,  H05K3/00

CPC classification number: H05K3/4697 ,  H05K3/0047

Abstract: The techniques described herein relate to an apparatus including: a support structure of an integrated circuit device; and an elongated cavity formed in the support structure of the integrated circuit device, wherein an interior of the elongated cavity is plated with a conductive material separated into a first power connection portion and a first ground connection portion.

公开(公告)号：US11425821B2

公开(公告)日：2022-08-23

申请号：US16547639

申请日：2019-08-22

Applicant: Cisco Technology, Inc.

Inventor： Amendra Koul ,  Mike Sapozhnikov ,  David Nozadze ,  Joel Goergen

IPC: H05K3/00 ,  H05K1/18 ,  H05K1/02 ,  G06F30/367 ,  G06F30/392 ,  G01R31/28

Abstract: A printed circuit board (PCB) includes a plurality of layers disposed at different depths of the PCB, circuit components disposed at different layers of the PCB, and a plurality of temperature measurement sensors located at one or more layers of the PCB, where each temperature measurement sensor is associated with a corresponding circuit component. A measured temperature is obtained at an embedded temperature measurement sensor located at an embedded layer within the PCB, and the measured temperature is correlated with an electrical property of an embedded circuit component located at the same embedded layer within the PCB as the embedded temperature measurement sensor. A plurality of moisture measurement sensors can also be located at one or more layers of the PCB to facilitate a measured moisture with an electrical property of an embedded circuit component.

公开(公告)号：US20210059055A1

公开(公告)日：2021-02-25

申请号：US16547639

申请日：2019-08-22

Applicant: Cisco Technology, Inc.

Inventor： Amendra Koul ,  Mike Sapozhnikov ,  David Nozadze ,  Joel Goergen

IPC: H05K3/00 ,  H05K1/18 ,  H05K1/02 ,  G06F17/50 ,  G01R31/28

Abstract: A printed circuit board (PCB) includes a plurality of layers disposed at different depths of the PCB, circuit components disposed at different layers of the PCB, and a plurality of temperature measurement sensors located at one or more layers of the PCB, where each temperature measurement sensor is associated with a corresponding circuit component. A measured temperature is obtained at an embedded temperature measurement sensor located at an embedded layer within the PCB, and the measured temperature is correlated with an electrical property of an embedded circuit component located at the same embedded layer within the PCB as the embedded temperature measurement sensor. A plurality of moisture measurement sensors can also be located at one or more layers of the PCB to facilitate a measured moisture with an electrical property of an embedded circuit component.

公开(公告)号：US20190036252A1

公开(公告)日：2019-01-31

申请号：US15661334

申请日：2017-07-27

Applicant: Cisco Technology, Inc.

Inventor： George Edward Curtis ,  Amrik S. Bains ,  Ken Naumann ,  Mike Sapozhnikov

IPC: H01R12/72 ,  H05K1/14 ,  H01R12/70 ,  H01R24/64

CPC classification number: H01R12/727 ,  H01R12/7023 ,  H01R12/722 ,  H01R13/514 ,  H01R13/518 ,  H01R13/659 ,  H01R24/64 ,  H01R25/006 ,  H01R2107/00 ,  H05K1/14

Abstract: A network connector assembly with an upper board member includes one or more upper coupling pins and a lower board member includes one or more lower coupling pins. The upper board member and lower board member each a plurality of sets of contact pins disposed on a respective top surface. A housing can be disposable over the upper board member and the lower board member forming one or more network couplers. Each of the one or more network couplers configured to receive one set of contact pins.

公开(公告)号：US20250151198A1

公开(公告)日：2025-05-08

申请号：US18434943

申请日：2024-02-07

Applicant: Cisco Technology, Inc.

Inventor： Joel Richard Goergen ,  Elizabeth Kochuparambil ,  Scott Hinaga ,  Kameron Rose Hurst ,  Mike Sapozhnikov ,  Shobhana Punjabi ,  David Nozadze ,  Marco Croci

IPC: H05K1/14 ,  H05K1/02 ,  H05K1/18 ,  H05K3/32

Abstract: Techniques to move high current power distribution layers for integrated circuit core power and serializer-deserializer (SERDES) power into a center area of the integrated circuit footprint. This provides a more reliable and higher current distribution into the center of a large integrated circuit footprint, without causing disruption of high speed signal routing or increased signal integrity burden to the high speed signals. Arrangements and methods for routing out the core power area of a main printed circuit board under an integrated circuit and replacing it with a custom power printed circuit board (power plug) that is attached by a metalized paste sintering process. This provides a more reliable and higher current distribution into the center of a large integrated circuit or other high-power component, without causing disruption of high speed signal routing.