公开(公告)号：US20200320013A1

公开(公告)日：2020-10-08

申请号：US16908182

申请日：2020-06-22

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F12/06 ,  G11C11/419 ,  G06F17/16 ,  G11C7/10 ,  G11C5/14 ,  G11C8/06

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US20190122721A1

公开(公告)日：2019-04-25

申请号：US16227771

申请日：2018-12-20

Applicant: Apple Inc.

Inventor： Edward M. McCombs

IPC: G11C11/4096 ,  G06F12/0875 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/4096 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/1028 ,  G06F2212/452 ,  G06F2212/6028 ,  G11C5/145 ,  G11C7/1096 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/419 ,  G11C2207/005

Abstract: Techniques for implementing a storage array write driver with a reduced-power boost circuit. An apparatus may include a bit cell configured to store data, a bit line circuit coupled to convey data to the bit cell, a write driver circuit configured to transmit write data to the bit cell via the bit line circuit, and a boost circuit that is distinct from the write driver circuit. The boost circuit may be selectively coupled to drive the bit line circuit below a ground voltage dependent on activation of a boost signal and the write data being in a logic low state. The boost circuit may also be coupled to the bit line circuit at a location that is closer to the bit cell than to the write driver circuit, and may be sized to discharge the bit line circuit without being sized to discharge internal capacitance of the write driver.

公开(公告)号：US20190095339A1

公开(公告)日：2019-03-28

申请号：US16124166

申请日：2018-09-06

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Ben D. Jarrett ,  Edward M. McCombs ,  Greg M. Hess

IPC: G06F12/10 ,  G06F17/16 ,  G11C11/419 ,  G06F12/06

CPC classification number: G06F12/10 ,  G06F12/06 ,  G06F17/16 ,  G11C5/144 ,  G11C5/148 ,  G11C7/1006 ,  G11C8/06 ,  G11C11/419

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

公开(公告)号：US09584122B1

公开(公告)日：2017-02-28

申请号：US15189134

申请日：2016-06-22

Applicant: Apple Inc.

Inventor： Edward M. McCombs

IPC: G11C5/14 ,  H03K19/00 ,  H03K3/356 ,  H03K19/096 ,  G11C11/40

CPC classification number: H03K19/0019 ,  G11C5/14 ,  G11C7/12 ,  G11C11/40 ,  G11C11/4074 ,  G11C11/4094 ,  H03K3/35613 ,  H03K19/0963

Abstract: Techniques for charge reuse in an integrated circuit. A processor may include a first logic circuit coupled to a source power supply node, a second logic circuit coupled to a destination power supply node, and a charge reuse circuit that selectively transfers charge from the first logic circuit to the second logic circuit. The charge reuse circuit may include an equalization device that selectively couples the source power supply node to the destination power supply node, and an equalization activation circuit that activates the equalization device in response to detecting assertion of an equalization control signal and further detecting that a voltage differential between the source power supply node and the destination power supply node is above a threshold value. The equalization activation circuit also prevents coupling of either the source power supply node or the destination power supply node to ground during activation of the equalization device.

Abstract translation: 集成电路中的电荷再利用技术。 处理器可以包括耦合到源电源节点的第一逻辑电路，耦合到目的地电源节点的第二逻辑电路以及选择性地将电荷从第一逻辑电路传输到第二逻辑电路的电荷重用电路。 电荷重复利用电路可以包括选择性地将源电源节点耦合到目的地电源节点的均衡装置，以及响应于检测到均衡控制信号的断言而激活均衡装置的均衡激活电路，并进一步检测电压 源电源节点和目的地供电节点之间的差异高于阈值。 均衡激活电路还防止在均衡设备激活期间源电源节点或目的地电源节点与地耦合。