公开(公告)号：US09367372B2

公开(公告)日：2016-06-14

申请号：US13920574

申请日：2013-06-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander Lyashevsky ,  Sudhanva Gurumurthi ,  Vilas Sridharan

IPC: G06F9/38 ,  G06F9/52 ,  G06F11/00 ,  G06F11/16

CPC classification number: G06F11/00 ,  G06F9/3851 ,  G06F9/52 ,  G06F11/1608 ,  G06F11/1633 ,  G06F11/1637 ,  G06F11/1654 ,  G06F11/1687 ,  G06F11/202 ,  G06F11/2038 ,  G06F11/2041 ,  G06F11/2048 ,  G06F2201/825 ,  G06F2201/83

Abstract: A system, method and computer program product to execute a first and a second work-item, and compare the signature variable of the first work-item to the signature variable of the second work-item. The first and the second work-items are mapped to an identifier via software. This mapping ensures that the first and second work-items execute exactly the same data for exactly the same code without changes to the underlying hardware. By executing the first and second work-items independently, the underlying computation of the first and second work-item can be verified. Moreover, system performance is not substantially affected because the execution results of the first and second work-items are compared only at specified comparison points.

Abstract translation: 一种用于执行第一和第二工作项目的系统，方法和计算机程序产品，并且将第一工作项目的签名变量与第二工作项目的签名变量进行比较。 第一个和第二个工作项通过软件映射到一个标识符。 此映射确保第一个和第二个工作项完全相同的数据完全相同的代码，而不会更改底层硬件。 通过独立地执行第一和第二工作项目，可以验证第一和第二工件的基础计算。 此外，系统性能基本上不受影响，因为第一和第二工作项目的执行结果仅在指定的比较点进行比较。

公开(公告)号：US09292418B2

公开(公告)日：2016-03-22

申请号：US14266131

申请日：2014-04-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Vilas Sridharan ,  Mark E. Wilkening ,  Sudhanva Gurumurthi

IPC: G06F9/44 ,  G06F11/36 ,  G06F11/34 ,  G06F9/48

CPC classification number: G06F11/3672 ,  G06F9/4843 ,  G06F11/34 ,  G06F11/3419 ,  G06F11/3471 ,  G06F11/3612

Abstract: The described embodiments include a program code testing system that determines the vulnerability of multi-threaded program code to soft errors. For multi-threaded program code, two to more threads from the program code may access shared architectural structures while the program code is being executed. The program code testing system determines accesses of architectural structures made by the two or more threads of the multi-threaded program code and uses the determined accesses to determine a time for which the program code is exposed to soft errors. From this time, the program code testing system determines a vulnerability of the program code to soft errors.

Abstract translation: 所描述的实施例包括程序代码测试系统，其确定多线程程序代码对软错误的脆弱性。 对于多线程程序代码，程序代码中的两个到更多的线程可以在执行程序代码时访问共享架构结构。 程序代码测试系统确定由多线程程序代码的两个或多个线程进行的架构结构的访问，并使用所确定的访问来确定程序代码暴露于软错误的时间。 从这时起，程序代码测试系统将程序代码的漏洞确定为软错误。

公开(公告)号：US20150067278A1

公开(公告)日：2015-03-05

申请号：US14013252

申请日：2013-08-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Sudhanva Gurumurthi ,  Vilas Sridharan

IPC: G06F3/06

CPC classification number: G06F12/0811

Abstract: In the described embodiments, a processor core (e.g., a GPU core) receives a section of program code to be executed in a transaction from another entity in a computing device. The processor core sends the section of program code to one or more compute units in the processor core to be executed in a first transaction and concurrently executed in a second transaction, thereby creating a “redundant transaction pair.” When the first transaction and the second transaction are completed, the processor core compares a read-set of the first transaction to a read-set of the second transaction and compares a write-set of the first transaction to a write-set of the second transaction. When the read-sets and the write-sets match and no transactional error condition has occurred, the processor core allows results from the first transaction to be committed to an architectural state of the computing device.

Abstract translation: 在所描述的实施例中，处理器核心（例如，GPU核心）从计算设备中的另一个实体接收要在事务中执行的程序代码部分。 处理器核心将程序代码段发送到处理器核心中的一个或多个计算单元，以在第一事务中执行并在第二事务中同时执行，从而创建“冗余事务对”。当第一事务和第二事务 处理器核心将第一事务的读取集合与第二事务的读取集进行比较，并将第一事务的写入集合与第二事务的写入集进行比较。 当读取集合和写入集合匹配并且没有发生事务错误条件时，处理器核心允许来自第一事务的结果被提交到计算设备的架构状态。

公开(公告)号：US12181959B2

公开(公告)日：2024-12-31

申请号：US16718168

申请日：2019-12-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Sudhanva Gurumurthi ,  Vilas K. Sridharan

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10

Abstract: A method and apparatus for predicting and managing a fault in memory includes detecting an error in data. The error is compared to one or more stored errors in a filter, and based upon the comparison, the error is predicted as a transient error or a permanent error for further action.

公开(公告)号：US20240264900A1

公开(公告)日：2024-08-08

申请号：US18625417

申请日：2024-04-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Divya Madapusi Srinivas Prasad ,  Sudhanva Gurumurthi ,  Yasuko Eckert ,  Jeffrey Richard Rearick ,  Sankaranarayanan Gurumurthy ,  Amitabh Mehra ,  Shidhartha Das ,  Alex W. Schaefer ,  Vikram Ramachandra ,  Vilas Sridharan

IPC: G06F11/07 ,  G06F1/30

CPC classification number: G06F11/0793 ,  G06F11/07 ,  G06F1/30 ,  G06F11/0721

Abstract: An exemplary computing device includes a plurality of circuits and/or a plurality of in-situ monitors configured to generate outputs that indicate one or more operating conditions of the circuits. The computing device also includes a system management unit configured to detect a potentially faulty voltage-to-frequency ratio implemented by one of the circuits based at least in part on one or more of the outputs. The system management unit is also configured to modify the potentially faulty voltage-to-frequency ratio based at least in part on one or more of the outputs. Various other devices, systems, and methods are also disclosed.

公开(公告)号：US20230394311A1

公开(公告)日：2023-12-07

申请号：US18236864

申请日：2023-08-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Sudhanva Gurumurthi ,  Abhinav Vishnu

IPC: G06N3/082 ,  G06N20/20 ,  G06T7/90 ,  G06N3/045 ,  G06V10/56 ,  G06V10/82 ,  G06V10/70

CPC classification number: G06N3/082 ,  G06N20/20 ,  G06T7/90 ,  G06N3/045 ,  G06V10/56 ,  G06V10/82 ,  G06V10/87

Abstract: A system comprising an electronic device that includes a processor is described. During operation, the processor acquires a full version of a neural network, the neural network including internal elements for processing instances of input image data having a set of color channels. The processor then generates, from the neural network, a set of sub-networks, each sub-network being a separate copy of the neural network with the internal elements for processing at least one of the color channels in instances of input image data removed, so that each sub-network is configured for processing a different set of one or more color channels in instances of input image data. The processor next provides the sub-networks for processing instances of input image data—and may itself use the sub-networks for processing instances of input image data.

公开(公告)号：US20230305923A1

公开(公告)日：2023-09-28

申请号：US17704474

申请日：2022-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Sudhanva Gurumurthi ,  Ganesh Suryanarayan Dasika

IPC: G06F11/10 ,  G06F11/07 ,  G06N20/00

CPC classification number: G06F11/1068 ,  G06F11/1004 ,  G06F11/0772 ,  G06F11/076 ,  G06N20/00

Abstract: A memory system uses error detection codes to detect when errors have occurred in a region of memory. A count of the number of errors is kept and a notification is output in response to the number of errors satisfying a threshold value. The notification is an indication to a host (e.g., a program accessing or managing a machine learning system) that the threshold number of errors have been detected in the region of memory. As long as the number of errors that have been detected in the region of memory remains under the threshold number no notification need be output to the host.

公开(公告)号：US11657004B2

公开(公告)日：2023-05-23

申请号：US17125978

申请日：2020-12-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Sudhanva Gurumurthi ,  Vilas K. Sridharan

IPC: G06F12/14 ,  G06F12/1009 ,  G06F21/79 ,  G06F12/0871 ,  G06F12/0882

CPC classification number: G06F12/1433 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1009 ,  G06F21/79

Abstract: A method and system for memory attack mitigation in a memory device includes receiving, at a memory controller, an allocation of a page in memory. One or more device controllers detects an aggressor-victim set within the memory. Based upon the detection, an address of the allocated page is identified for further action.

公开(公告)号：US11573853B2

公开(公告)日：2023-02-07

申请号：US17218535

申请日：2021-03-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Vilas Sridharan ,  Sudhanva Gurumurthi

IPC: G06F3/06 ,  G06F11/10

Abstract: Error checking data used in offloaded operations is disclosed. A remote execution device receives a request from a host to store a data block in a memory region. The data block includes data and host-generated error checking information for the data. The remote execution device updates the data block by overwriting the host-generated error checking information with locally generated error checking information for the data. The data block is then stored in the memory region.

公开(公告)号：US20220206899A1

公开(公告)日：2022-06-30

申请号：US17133843

申请日：2020-12-24

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Nuwan Jayasena ,  Sudhanva Gurumurthi ,  Shaizeen Aga ,  Shrikanth Ganapathy

IPC: G06F11/14 ,  G06F11/07 ,  G06F9/30 ,  G06F9/38

Abstract: Methods and processing devices are provided for error protection to support instruction replay for executing idempotent instructions at a processing in memory PIM device. The processing apparatus includes a PIM device configured to execute an idempotent instruction. The processing apparatus also includes a processor, in communication with the PIM device, configured to issue the idempotent instruction to the PIM device for execution at the PIM device and reissue the idempotent instruction to the PIM device when one of execution of the idempotent instruction at the PIM device results in an error and a predetermined latency period expires from when the idempotent instruction is issued.