公开(公告)号：US09236305B2

公开(公告)日：2016-01-12

申请号：US14158529

申请日：2014-01-17

申请人： Applied Materials, Inc.

发明人： Wei-Sheng Lei ,  Saravjeet Singh ,  Jivko Dinev ,  Aparna Iyer ,  Brad Eaton ,  Ajay Kumar

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/027 ,  H01L21/311 ,  H01J37/32 ,  H01L21/683 ,  B23K26/36 ,  B23K26/40

CPC分类号： H01L21/78 ,  B23K26/364 ,  B23K26/40 ,  B23K26/402 ,  B23K2103/172 ,  B23K2103/50 ,  H01J37/32009 ,  H01L21/0271 ,  H01L21/3065 ,  H01L21/31105 ,  H01L21/31127 ,  H01L21/6836 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381

摘要： Laser and plasma etch wafer dicing where a mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The semiconductor wafer is coupled to a film frame by an adhesive film. The mask is patterned by laser scribing to provide a patterned mask with gaps. The laser scribing exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is plasma etched through the gaps in the patterned mask while the film frame is maintained at an acceptably low temperature with a chamber shield ring configured to sit beyond the wafer edge and cover the frame. The shield ring may be raised and lowered, for example, on lifter pins to facilitate transfer of the wafer on frame.

摘要翻译： 激光和等离子体蚀刻晶片切割，其中形成掩模以覆盖形成在晶片上的IC，以及提供与IC的界面的任何凸块。 半导体晶片通过粘合膜耦合到胶片框架。 通过激光划线将掩模图案化以提供具有间隙的图案化掩模。 激光划线使半导体晶片的区域露出在形成有IC的薄膜层的下方。 半导体晶片通过图案化掩模中的间隙进行等离子体蚀刻，同时膜框架被保持在可接受的低温下，腔室屏蔽环被配置为超过晶片边缘并覆盖框架。 屏蔽环可以升高和降低，例如在升降器销上，以促进晶片在框架上的传送。

公开(公告)号：US08975162B2

公开(公告)日：2015-03-10

申请号：US14095824

申请日：2013-12-03

申请人： Applied Materials, Inc.

发明人： Wei-Sheng Lei ,  Brad Eaton ,  Aparna Iyer ,  Saravjeet Singh ,  Madhava Rao Yalamanchili ,  Ajay Kumar

IPC分类号： H01L21/00 ,  H01L21/822 ,  H01L21/78 ,  H01L21/308 ,  H01L21/683

CPC分类号： H01L21/822 ,  B23K26/0624 ,  B23K26/18 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  B23K2103/50 ,  H01L21/3081 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. For example, a method includes applying a protection tape to a wafer front side, the wafer having a dicing tape attached to the wafer backside. The dicing tape is removed from the wafer backside to expose a die attach film disposed between the wafer backside and the dicing tape. Alternatively, if no die attach film is initially disposed between the wafer backside and the dicing tape, a die attach film is applied to the wafer backside at this operation. A water soluble mask is applied to the wafer backside. Laser scribing is performed on the wafer backside to cut through the mask, the die attach film and the wafer, including all layers included within the front side and backside of the wafer. A plasma etch is performed to treat or clean surfaces of the wafer exposed by the laser scribing. A wafer backside cleaning is performed and a second dicing tape is applied to the wafer backside. The protection tape is the removed from the wafer front side.

摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 例如，一种方法包括将保护带施加到晶片正面，所述晶片具有附接到晶片背面的切割带。 切割胶带从晶片背面去除，以露出设置在晶片背面和切割胶带之间的管芯附着膜。 或者，如果在晶片背面和切割带之间不设置管芯附着膜，则在该操作中将芯片附着膜施加到晶片背面。 将水溶性掩模施加到晶片背面。 在晶片背面进行激光划线，以切割掩模，芯片附着膜和晶片，包括包括在晶片的正面和背面内的所有层。 执行等离子体蚀刻以处理或清洁由激光划线暴露的晶片的表面。 执行晶片背面清洁，并且将第二切割带施​​加到晶片背面。 保护带从晶片正面去除。

公开(公告)号：US20210265134A1

公开(公告)日：2021-08-26

申请号：US17157224

申请日：2021-01-25

申请人： Applied Materials, Inc.

发明人： Saravjeet Singh ,  Kenneth D. Schatz ,  Alan Tso ,  Marlin Wijekoon ,  Dimitri Kioussis

IPC分类号： H01J37/32 ,  H01L21/02

摘要： The present technology includes improved gas distribution designs for forming uniform plasmas during semiconductor processing operations or for treating the interior of semiconductor processing chambers. While conventional gas distribution assemblies may receive a specific reactant or reactant ratio which is then distributed into the plasma region, the presently described technology allows for improved control of the reactant input distribution. The technology allows for separate flows of reactants to different regions of the plasma to offset any irregularities observed in process uniformity. A first precursor may be delivered to the center of the plasma above the center of the substrate/pedestal while a second precursor may be delivered to an outer portion of the plasma above an outer portion of the substrate/pedestal. In so doing, a substrate residing on the pedestal may experience a more uniform etch or deposition profile across the entire surface.

公开(公告)号：US10920319B2

公开(公告)日：2021-02-16

申请号：US16245698

申请日：2019-01-11

申请人： Applied Materials, Inc.

发明人： Laksheswar Kalita ,  Soonam Park ,  Dmitry Lubomirsky ,  Tien Fak Tan ,  LokKee Loh ,  Saravjeet Singh ,  Tae Won Kim

IPC分类号： C23C16/455 ,  C23C16/34 ,  H01L21/3213 ,  H01J37/32 ,  H01L21/285 ,  C23C16/458

摘要： Exemplary semiconductor processing chamber showerheads may include a dielectric plate characterized by a first surface and a second surface opposite the first surface. The dielectric plate may define a plurality of apertures through the dielectric plate. The dielectric plate may define a first annular channel in the first surface of the dielectric plate, and the first annular channel may extend about the plurality of apertures. The dielectric plate may define a second annular channel in the first surface of the dielectric plate. The second annular channel may be formed radially outward from the first annular channel. The showerheads may also include a conductive material embedded within the dielectric plate and extending about the plurality of apertures without being exposed by the apertures. The conductive material may be exposed at the second annular channel.

公开(公告)号：US10811232B2

公开(公告)日：2020-10-20

申请号：US15671909

申请日：2017-08-08

申请人： Applied Materials, Inc.

发明人： Deepak Doddabelavangala Srikantaiah ,  Sheshraj L. Tulshibagwale ,  Saravjeet Singh ,  Alexander Tam

IPC分类号： H01J37/32 ,  B05B1/00 ,  B05B1/18

摘要： Embodiments of the disclosure relate to a multi-plate faceplate having a first plate and a second plate. The first plate has a plurality of first plate openings. The second plate has a first surface, an opposed second surface and a plurality of second plate openings extending therethrough. The first surface is mechanically coupled to the first plate. A second plate opening has a conical portion configured to be fluidly coupled to a first plate opening and decreasing in cross-section in the depth direction thereof from the second surface. A surface of the conical portion is coated with a protective coating adjacent to the first and second surfaces. In another embodiment, the first plate has a protrusion extending therefrom into a recess formed inwardly of the first surface. The protrusion has a passage extending therethrough fluidly connected to the recess, which is fluidly connected to the second plate opening.

公开(公告)号：US20200118880A1

公开(公告)日：2020-04-16

申请号：US16706541

申请日：2019-12-06

申请人： Applied Materials, Inc.

发明人： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC分类号： H01L21/822 ,  H01L21/3065 ,  B23K26/36 ,  H01L23/544 ,  H01L21/67 ,  H01J37/32 ,  H01L21/78 ,  H01L21/308

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US20200087788A1

公开(公告)日：2020-03-19

申请号：US16132796

申请日：2018-09-17

申请人： APPLIED MATERIALS, INC.

发明人： Tien Fak Tan ,  Saravjeet Singh ,  Tae Won Kim

IPC分类号： C23C16/455 ,  C23C16/509

摘要： Exemplary semiconductor showerheads may include a first plate characterized by a first surface in which a plurality of first apertures are defined, and further characterized by a second surface opposite the first surface and from which extends a plurality of annular members. Each annular member of the plurality of annular members may extend from a separate first aperture of the plurality of first apertures. A channel may be defined by each first aperture and corresponding annular member. The showerheads may also include a second plate coupled with the first plate and characterized by a first surface facing the first plate and a second surface opposite the first surface. A plurality of second apertures may be defined through the second plate within an internal area of the second plate. Each annular member of the plurality of annular members may extend within a separate second aperture of the plurality of second apertures.

公开(公告)号：US10566238B2

公开(公告)日：2020-02-18

申请号：US16193886

申请日：2018-11-16

申请人： Applied Materials, Inc.

发明人： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC分类号： H01L21/00 ,  H01L21/822 ,  H01L21/308 ,  H01L21/67 ,  H01L21/78 ,  H01J37/32 ,  H01L23/544 ,  B23K26/36 ,  H01L21/3065 ,  H01L21/683

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US20190088549A1

公开(公告)日：2019-03-21

申请号：US16193886

申请日：2018-11-16

申请人： Applied Materials, Inc.

发明人： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC分类号： H01L21/822 ,  H01J37/32 ,  H01L21/67 ,  H01L21/3065 ,  B23K26/36 ,  H01L23/544 ,  H01L21/78 ,  H01L21/308 ,  H01L21/683

摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US09978632B2

公开(公告)日：2018-05-22

申请号：US14730192

申请日：2015-06-03

申请人： Applied Materials, Inc.

发明人： Khiem Nguyen ,  Saravjeet Singh ,  Amitabh Sabharwal

IPC分类号： H01L21/677 ,  H01L21/687 ,  H01L21/67 ,  C23C16/458 ,  H01J37/32

CPC分类号： H01L21/68742 ,  C23C16/458 ,  H01J37/32715 ,  H01J37/32788

摘要： The present disclosure provides a substrate support assembly includes a substrate pedestal having an upper surface for receiving and supporting a substrate, a cover plate disposed on the substrate support pedestal, and two or more lift pins movably disposed through the substrate support pedestal and the cover plate. The cover plate includes a disk body having a central opening. The two or more lift pins are self supportive. Each of the two or more lift pins comprises one or more contact pads, and the contact pads of the lift pins extend into to the central opening of the cover plate to receive and support a substrate at an edge region of the substrate.