公开(公告)号：US07727894B2

公开(公告)日：2010-06-01

申请号：US11649015

申请日：2007-01-03

Applicant: Sailesh Chittipeddi ,  Sailesh Merchant

Inventor： Sailesh Chittipeddi ,  Sailesh Merchant

IPC: H01L21/311 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L23/53295 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a metallization level having a dual damascene trench structure formed in a layer of dielectric material. The dielectric material has an upper surface with a first degree of planarity. The metallization level includes a conductive layer formed in the trench structure with an upper surface characterized by the same level of planarity as the dielectric material upper surface. In certain embodiments, the upper surface of the conductive layer is substantially coplanar with the dielectric material upper surface.

Abstract translation: 集成电路结构包括具有形成在电介质材料层中的双镶嵌沟槽结构的金属化层。 电介质材料具有第一平面度的上表面。 金属化层包括形成在沟槽结构中的导电层，其上表面具有与电介质材料上表面相同的平面度水平。 在某些实施例中，导电层的上表面与电介质材料上表面基本共面。

公开(公告)号：US20070069368A1

公开(公告)日：2007-03-29

申请号：US11235920

申请日：2005-09-27

Applicant: Vance Archer ,  Kouros Azimi ,  Daniel Chesire ,  Warren Gladden ,  Seung Kang ,  Taeho Kook ,  Sailesh Merchant ,  Vivian Ryan

Inventor： Vance Archer ,  Kouros Azimi ,  Daniel Chesire ,  Warren Gladden ,  Seung Kang ,  Taeho Kook ,  Sailesh Merchant ,  Vivian Ryan

IPC: H01L23/34

CPC classification number: H01L23/36 ,  H01L21/4871 ,  H01L25/165 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00

Abstract: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.

Abstract translation: 一种集成电路装置，其包括冶金结合以增强对散热器的热传导。 在半导体器件中，集成电路管芯的表面冶金地结合到散热器的表面。 在制造器件的示例性方法中，封装衬底的上表面包括内部区域和周边区域。 集成电路管芯位于衬底表面上，并且集成电路管芯的第一表面被放置成与封装衬底接触。 金属层形成在集成电路管芯的第二相对表面上。 预成型件定位在金属层上，并且散热器位于预制件上。 用预成型件形成接合层，将散热器冶金结合到集成电路管芯的第二表面。

公开(公告)号：US07135733B2

公开(公告)日：2006-11-14

申请号：US10195935

申请日：2002-07-16

Applicant: Stephen Downey ,  Edward Harris ,  Sailesh Merchant

Inventor： Stephen Downey ,  Edward Harris ,  Sailesh Merchant

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L23/5223 ,  H01L27/0688 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a capacitor for use in a semiconductor device having a damascene interconnect structure, such as a dual damascene interconnect, formed over a substrate of a semiconductor wafer. In one particularly advantageous embodiment, the capacitor, comprises a first capacitor electrode, such as copper, comprised of a portion of the damascene interconnect structure, an insulator layer formed on the damascene interconnect structure wherein the insulator layer is a passivation layer, such as silicon nitride. The passivation layer may be an outermost or final passivation layer, or it may be an interlevel passivation layer. The capacitor further includes a second capacitor electrode comprised of a conductive layer, such as aluminum, that is formed on at least a portion of the insulator layer.

公开(公告)号：US20060192584A1

公开(公告)日：2006-08-31

申请号：US11403750

申请日：2006-04-13

Applicant: Seung Kang ,  Subramanian Karthikeyan ,  Sailesh Merchant

Inventor： Seung Kang ,  Subramanian Karthikeyan ,  Sailesh Merchant

IPC: G01R31/26

CPC classification number: G01R31/2877 ,  G01R31/2853 ,  G01R31/2856 ,  H01L22/32

Abstract: Method and test structures for determining heating effects in a test semiconductor device (10) are provided. The test device may include a first conductive metal structure (151-156) for accepting a flow of electric current that causes a heating effect. The test device may further include a second conductive metal structure proximate (121-126) the first conductive structure for obtaining resistivity changes in response to the heating effect. The resistivity changes are indicative of temperature changes due to the heating effect.

Abstract translation: 提供了用于确定测试半导体器件（10）中的加热效应的方法和测试结构。 测试装置可以包括用于接受引起加热效应的电流的第一导电金属结构（15 SUB-15 6）。 测试装置还可以包括靠近第一导电结构的第二导电金属结构，用于响应于加热效应而获得电阻率变化。 电阻率变化表示由于加热效应引起的温度变化。

公开(公告)号：US20060066337A1

公开(公告)日：2006-03-30

申请号：US10953292

申请日：2004-09-29

Applicant: Seung Kang ,  Subramanian Karthikeyan ,  Sailesh Merchant

Inventor： Seung Kang ,  Subramanian Karthikeyan ,  Sailesh Merchant

IPC: G01R31/26

CPC classification number: G01R31/2877 ,  G01R31/2853 ,  G01R31/2856 ,  H01L22/32

Abstract: Method and test structures for determining heating effects in a test semiconductor device (10) are provided. The test device may include a first conductive metal structure (151-156) for accepting a flow of electric current that causes a heating effect. The test device may further include a second conductive metal structure proximate (121-126) the first conductive structure for obtaining resistivity changes in response to the heating effect. The resistivity changes are indicative of temperature changes due to the heating effect.

公开(公告)号：US20060066327A1

公开(公告)日：2006-03-30

申请号：US10953291

申请日：2004-09-29

Applicant: Mark Bachman ,  Daniel Chesire ,  Taeho Kook ,  Sailesh Merchant

Inventor： Mark Bachman ,  Daniel Chesire ,  Taeho Kook ,  Sailesh Merchant

IPC: G01R31/02

CPC classification number: H01L24/10 ,  H01L22/32 ,  H01L24/13 ,  H01L2224/0392 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An interface assembly (20) and method for testing a semiconductor wafer prior to performing a flip chip bumping process are provided. The interface assembly includes a flip chip bonding pad (24) having a region (28) for performing the bumping process. A test pad (22) is integrally constructed with the bonding pad and includes a probe region (26) for performing wafer-level testing prior to performing the bumping process. The integral construction of the bonding and testing pads avoids, for example, an introduction of propagation delays to test signals passing therethrough, thereby improving the accuracy and reliability of wafer test results.

Abstract translation: 提供了一种用于在执行倒装芯片碰撞处理之前测试半导体晶片的界面组件（20）和方法。 接口组件包括具有用于执行碰撞处理的区域（28）的倒装芯片焊盘（24）。 测试焊盘（22）与接合焊盘一体构成，并且包括用于在执行碰撞过程之前进行晶片级测试的探针区域（26）。 焊接和测试焊盘的整体结构避免了例如引入传播延迟来测试通过其的信号，从而提高了晶片测试结果的准确性和可靠性。

公开(公告)号：US06890827B1

公开(公告)日：2005-05-10

申请号：US09384503

申请日：1999-08-27

Applicant: Seungmoo Choi ,  Sailesh Merchant ,  Pradip K. Roy

Inventor： Seungmoo Choi ,  Sailesh Merchant ,  Pradip K. Roy

IPC: H01L21/8242 ,  H01L29/786 ,  H01L21/331

CPC classification number: H01L29/78696 ,  H01L27/10873 ,  H01L29/78621 ,  Y10S438/979

Abstract: To address the above-discussed deficiencies of the prior art, the present invention provides an integrated circuit formed on a semiconductor wafer, comprising a doped base substrate; an insulator layer formed over the doped base substrate; and a doped ultra thin active layer formed on the insulator layer, the ultra thin active layer including a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate. The present invention therefore provides a semiconductor wafer that provides a doped ultra thin active layer. The lower Ioff in the DRAM transistor allows for lower heat dissipation, and the overall power requirement is decreased. Thus, the present invention provides a lower Ioff with reasonably good ion characteristics.

Abstract translation: 为了解决现有技术的上述缺陷，本发明提供一种形成在半导体晶片上的集成电路，包括掺杂的基底; 在所述掺杂的基底衬底上形成的绝缘体层; 以及形成在所述绝缘体层上的掺杂的超薄有源层，所述超薄有源层包括栅极氧化物，形成在所述栅极氧化物上的栅极以及形成在所述超薄有源层中并且邻近所述栅极的源极和漏极区域。 因此，本发明提供一种提供掺杂的超薄有源层的半导体晶片。 DRAM晶体管中的较低Ioff允许较低的散热，并且整体功率需求降低。 因此，本发明提供具有相当好的离子特性的较低的Ioff。

公开(公告)号：US20050035466A1

公开(公告)日：2005-02-17

申请号：US10939292

申请日：2004-09-10

Applicant: Sailesh Chittipeddi ,  Sailesh Merchant

Inventor： Sailesh Chittipeddi ,  Sailesh Merchant

IPC: H01L21/60 ,  H01L21/607 ,  H01L23/485 ,  H01L29/40

CPC classification number: H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/04042 ,  H01L2224/05681 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/45624 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/78301 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85375 ,  H01L2224/85948 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01066 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/00 ,  H01L2224/48781 ,  H01L2224/48681 ,  H01L2224/45147 ,  H01L2924/00015 ,  H01L2924/013 ,  H01L2924/01006

Abstract: The present invention uses wire bonding technology to bond interconnect materials that oxidize easily by using a wire with stable oxidation qualities. A passivation layer is formed on the semiconductor substrate to encapsulate the bonding pad made from the interconnect material such that the wire bonds with the passivation layer itself, not with the interconnect material. The passivation layer is selected to be a material that is metallurgically stable when bonded to the interconnect material. Since the wire is stable compared with the interconnect material, i.e., it does not readily corrode, a reliable mechanical and electrical connection is provided between the semiconductor device (interconnect material) and the wire, with the passivation layer disposed therebetween.

Abstract translation: 本发明使用引线接合技术，通过使用具有稳定的氧化特性的导线，可以容易地接合易氧化的互连材料。 在半导体衬底上形成钝化层以封装由互连材料制成的接合焊盘，使得引线与钝化层本身而不是与互连材料结合。 钝化层选择为当结合到互连材料时是冶金稳定的材料。 由于线与互连材料相比是稳定的，即不易腐蚀，所以在半导体器件（互连材料）和导线之间提供可靠的机械和电连接，其中钝化层位于它们之间。