公开(公告)号：US20090023258A1

公开(公告)日：2009-01-22

申请号：US11779270

申请日：2007-07-17

Applicant: Chia-Wen Liang ,  Cheng-Tung Huang ,  Shyh-Fann Ting ,  Chih-Chiang Wu ,  Shih-Chieh Hsu ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Meng-Yi Wu ,  Wen-Han Hung ,  Tzyy-Ming Cheng

Inventor： Chia-Wen Liang ,  Cheng-Tung Huang ,  Shyh-Fann Ting ,  Chih-Chiang Wu ,  Shih-Chieh Hsu ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Meng-Yi Wu ,  Wen-Han Hung ,  Tzyy-Ming Cheng

IPC: H01L21/8238

CPC classification number: H01L21/823864 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

Abstract: A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.

Abstract translation: 制造CMOS晶体管的方法包括在栅极结构形成，轻掺杂漏极形成，源极/漏极注入或SEG工艺之后交替执行的蚀刻反应工艺，以蚀刻覆盖并保护第一类型栅极结构的硬掩模层，以及 减少覆盖第一类型栅极结构的硬掩模和第二类型栅极结构之间的厚度偏差。 因此，防止了由于厚度偏差导致的间隔物，STI和栅极结构的轮廓的损坏。

公开(公告)号：US20080220574A1

公开(公告)日：2008-09-11

申请号：US11681987

申请日：2007-03-05

Applicant: Li-Shian Jeng ,  Cheng-Tung Huang ,  Shyh-Fann Ting ,  Wen-Han Hung ,  Kun-Hsien Lee ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

Inventor： Li-Shian Jeng ,  Cheng-Tung Huang ,  Shyh-Fann Ting ,  Wen-Han Hung ,  Kun-Hsien Lee ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.

Abstract translation: 提供了制造互补金属氧化物半导体（CMOS）器件的方法。 在衬底的第一区域中形成包括使用半导体化合物作为主要材料的源/漏区的第一导电型MOS晶体管。 在基板的第二区域中形成第二导电型MOS晶体管。 接下来，执行预非晶体注入（PAI）工艺以使第二导电型MOS晶体管的栅极导电层非晶化。 此后，在第二区域中的基板上形成应力转移方案（STS），以在栅极导电层中产生应力。 之后，进行快速热退火（RTA）处理以激活源极/漏极区域中的掺杂剂。 然后，STS被删除。

公开(公告)号：US06580641B2

公开(公告)日：2003-06-17

申请号：US10065590

申请日：2002-10-31

Applicant: Meng-Yi Wu ,  Kung-Hong Lee ,  Fu-Yuan Chen ,  Hsin-Fen Chou ,  Ching-Song Yang ,  Ya-Chin Kin ,  Ching-Hsiang Hsu

Inventor： Meng-Yi Wu ,  Kung-Hong Lee ,  Fu-Yuan Chen ,  Hsin-Fen Chou ,  Ching-Song Yang ,  Ya-Chin Kin ,  Ching-Hsiang Hsu

IPC: G11C1134

CPC classification number: H01L27/11553 ,  G11C16/0433 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825

Abstract: A method of forming and operating a trench split-gate non-volatile flash memory cell structure. The auxiliary gate of the structure is formed inside a trench on one side of the gate and the source terminal is underneath the auxiliary gate, thereby reducing overall area occupation of the auxiliary gate and the source terminal relative to the cell and increasing packing density. By enclosing the common source terminal inside a deep N-well layer, source resistance for reading data from the cell is reduced and the process of etching out a contact opening is simplified. The structure also ensures the injection of most hot electrons into the floating gate, thereby increasing execution speed.

公开(公告)号：US20130121079A1

公开(公告)日：2013-05-16

申请号：US13295102

申请日：2011-11-14

Applicant: Meng-Yi Wu ,  Ching-Sung Yang

Inventor： Meng-Yi Wu ,  Ching-Sung Yang

IPC: G11C16/04 ,  H01L29/78

CPC classification number: H01L29/792 ,  G11C16/0433 ,  H01L27/1157 ,  H01L29/518

Abstract: The present invention provides a NOR flash memory cell. The NOR flash memory cell includes a first transistor, a second transistor and at least one third transistor. The first transistor has a control terminal, a first terminal and a second terminal. The control terminal used to receive a word line signal and the first terminal used to receive a bit line signal. A gate of the first transistor comprises a silicon-rich nitride layer and an oxide layer, wherein the silicon-rich nitride layer is buried in the oxide layer. A control terminal of the second transistor used to receive a read signal. A second terminal of the second transistor used to transport a source line signal according to the read signal. The third transistor coupled between the first transistor and the bit line signal, and a control terminal of the third transistor receives a midway control signal.

Abstract translation: 本发明提供了一种NOR闪存单元。 NOR闪存单元包括第一晶体管，第二晶体管和至少一个第三晶体管。 第一晶体管具有控制端子，第一端子和第二端子。 用于接收字线信号的控制终端和用于接收位线信号的第一终端。 第一晶体管的栅极包括富含硅的氮化物层和氧化物层，其中富含硅的氮化物层被掩埋在氧化物层中。 用于接收读取信号的第二晶体管的控制端。 第二晶体管的第二端子用于根据读取信号传输源极线信号。 耦合在第一晶体管和位线信号之间的第三晶体管，以及第三晶体管的控制端子接收中途控制信号。

公开(公告)号：US07927954B2

公开(公告)日：2011-04-19

申请号：US11678627

申请日：2007-02-26

Applicant: Shyh-Fann Ting ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Meng-Yi Wu ,  Tsai-Fu Hsiao ,  Shu-Yen Chan

Inventor： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Meng-Yi Wu ,  Tsai-Fu Hsiao ,  Shu-Yen Chan

IPC: H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.

Abstract translation: 公开了制造应变硅晶体管的方法。 首先，提供半导体衬底，并且在半导体衬底上设置栅极结构和围绕栅极结构的间隔物。 然后在隔离物周围的半导体衬底中形成源极/漏极区域，并且执行第一快速热退火处理以激活源极/漏极区域内的掺杂剂。 执行蚀刻工艺以在栅极结构周围形成凹陷，并且执行选择性外延生长工艺以在凹部中形成外延层。 执行第二快速热退火处理以重新定义源/漏区域内的掺杂剂的分布并修复掺杂剂的损坏的键。

公开(公告)号：US07888223B2

公开(公告)日：2011-02-15

申请号：US11692609

申请日：2007-03-28

Applicant: Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

Inventor： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659

Abstract: A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.

Abstract translation: 制造p型沟道FET的方法包括在衬底上形成栅极。 然后，执行PAI离子注入工艺。 此外，进行袋注入工艺以形成袋区域。 此后，执行第一共注入工艺以限定源极/漏极延伸区域深度分布。 然后，形成p型源极/漏极延伸区域。 之后，执行第二共注入处理以限定源极/漏极区域深度分布。 此后，进行原位掺杂外延生长工艺以形成用作p型源/漏区的掺杂半导体化合物。

公开(公告)号：US20090117701A1

公开(公告)日：2009-05-07

申请号：US11934053

申请日：2007-11-01

Applicant: Meng-Yi Wu ,  Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Chung-Min Shih ,  Yao-Chin Cheng ,  Tzyy-Ming Cheng

Inventor： Meng-Yi Wu ,  Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Chung-Min Shih ,  Yao-Chin Cheng ,  Tzyy-Ming Cheng

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/28035 ,  H01L21/28202 ,  H01L21/28247

Abstract: A method for manufacturing a MOS transistor includes performing a thermal treatment to repair damaged substrate before forming source/drain extension regions, accordingly negative bias temperature instability (NBTI) is reduced. Since the thermal treatment is performed before forming the source/drain extension regions, heat budget for forming the source/drain extension regions and junction depth and junction profile of the source/drain extension would not be affected. Therefore the provided method for manufacturing a MOS transistor is capable of reducing short channel effect and possesses a superior process compatibility.

Abstract translation: 制造MOS晶体管的方法包括在形成源极/漏极延伸区域之前执行热处理以修复损坏的衬底，因此减小了负偏压温度不稳定性（NBTI）。 由于在形成源极/漏极延伸区域之前进行热处理，因此不会影响用于形成源极/漏极延伸区域的热量预算和源极/漏极延伸部的结深度和结型材。 因此，所提供的制造MOS晶体管的方法能够减少短沟道效应并具有优异的工艺兼容性。