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公开(公告)号：US20230065526A1
公开(公告)日：2023-03-02
申请号：US17887573
申请日：2022-08-15
Inventor： Jiakun Wang , Bing Wu
IPC: H01L29/66 , H01L29/10 , H01L29/40 , H01L29/78 , H01L21/265 , H01L21/266
Abstract: Disclosed is a split-gate power MOS device and a manufacturing method thereof. The method comprises: forming a trench in an epitaxial layer on a substrate; forming a first insulation layer on a surface of the epitaxial layer and in the trench; filling a cavity with polycrystalline silicon, performing back-etching; performing spin-coating on the first gate conductor layer to form a second insulation layer; forming a mask on the second insulation layer, removing a portion of the first insulation layer, to expose an upper portion of the trench; forming a gate oxide layer on a sidewall of the upper portion of the trench and the surface of the epitaxial layer; and forming a second gate conductor layer in the upper portion of the trench. According to the present disclosure, voltage withstand and electric leakage between the first gate conductor layer and the second gate conductor layer are reduced.
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公开(公告)号：US20230038280A1
公开(公告)日：2023-02-09
申请号：US17881736
申请日：2022-08-05
Inventor： Hui Chen
Abstract: Disclosed is a silicon carbide MOSFET device and a manufacturing method thereof. The manufacturing method comprises: forming a source region in an epitaxial layer; forming a body region in the epitaxial layer; forming a gate structure, comprising a gate dielectric layer, a gate conductor layer and an interlayer dielectric layer; forming an opening in the interlayer dielectric layer to expose the source region; forming a source contact connected to the source region via the opening, wherein an ion implantation angle of the ion implantation process is controlled to make a transverse extension range of the body region larger than a transverse extension range of the source region, so that a channel that extends transversely is formed by a portion, which is peripheral to the source region, of the body region, and at least a portion of the gate conductor layer is located above the channel.
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公开(公告)号：US20250072047A1
公开(公告)日：2025-02-27
申请号：US18801861
申请日：2024-08-13
Inventor： Yanggang OU , Jiakun WANG
IPC: H01L29/78 , H01L29/06 , H01L29/417 , H01L29/66
Abstract: A semiconductor device includes a current spreading layer, a gate trench, a gate electrode, a first body region, a first source region, a second body region and a second source region. The first body region is beneath and in contact with the gate trench. The first source region is formed in the first body region. The second body region extends from a first surface of the current spreading layer into the current spreading layer and adjoins a first sidewall of the gate trench. The second source region is formed in the second body region and adjoins the first sidewall of the gate trench.
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公开(公告)号：US12176406B2
公开(公告)日：2024-12-24
申请号：US17113305
申请日：2020-12-07
Inventor： Jiakun Wang
IPC: H01L29/423 , H01L29/40 , H01L29/417 , H01L29/66 , H01L29/78
Abstract: A trench MOSFET can include: a semiconductor layer having a first doping type; a trench extending from an upper surface of the semiconductor layer to internal portion of the semiconductor layer; insulating layers and electrode conductors located in the trench; a body region having a second doping type in an upper region of the semiconductor layer adjacent to the trench; and a floating region having the first doping type located in a predetermined position of the semiconductor layer adjacent to both sides of the trench, where the floating region is located below the body region and is separated from the body region.
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公开(公告)号：US20240339922A1
公开(公告)日：2024-10-10
申请号：US18404674
申请日：2024-01-04
Inventor： Beomhee Park , Jaihyuk Choi , Jung Su Choi , Hyeon Deok Jeon
Abstract: The switching converter equipped with negative current tracking control includes a switching transistor whose drain is connected to an input power supply, a rectifying transistor whose drain is connected to a source of the switching transistor and whose source is connected to a ground, an inductor having one end connected to the source of the switching transistor and the drain of the rectifying transistor, an output capacitor having a first end connected to the other end of the inductor and a second end connected to a ground, a PWM controller that outputs a PWM control signal to a gate of the switching transistor and a gate of the rectifying transistor, a zero current detector that detects zero crossing of an inductor current flowing through the inductor, and a negative current tracking controller that variably adjusts an offset of the zero current detector.
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Patent Agency Ranking
公开(公告)号：US20240178058A1
公开(公告)日：2024-05-30
申请号：US18523509
申请日：2023-11-29
Inventor： Chenhan Wang
IPC: H01L21/768 , H01L29/66 , H01L29/78
CPC classification number: H01L21/76805 , H01L29/6659 , H01L29/7802
Abstract: A semiconductor device includes an epitaxial layer and a doped region located in the epitaxial layer. A contact structure of the semiconductor device includes: an interlayer dielectric layer, arranged on the epitaxial layer; a contact hole, including a first portion extending through the interlayer dielectric layer and a second portion extending into the doped region, where a size of the first portion is greater than a size of the second portion, the second portion is open on a bottom surface of the first portion, and a bottom surface of the second portion is arranged in the doped region; a contact layer, including a first contact layer arranged on the bottom surface of the first portion and a second contact layer arranged on the bottom surface of the second portion; and a conductive channel, arranged in the contact hole and contacting the contact layer.
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公开(公告)号：US20240154616A1
公开(公告)日：2024-05-09
申请号：US18503959
申请日：2023-11-07
Inventor： Young Jae Chang , Sung Ryong Lee , Jae Sam Shim
CPC classification number: H03L7/087 , H03L7/0991 , H03L7/1075
Abstract: A clock and data recovery device includes an equalizer that compensates for channel loss of input data, a phase detector that compares data output from the equalizer and a fed back clock and outputs an up signal and a down signal, a charge pump that operates according to the up signal and the down signal to output a control signal, a loop filter that removes a high-frequency component included in the control signal output from the charge pump, a voltage-controlled oscillator that changes a frequency of the clock and outputs the clock according to the control signal from which the high-frequency component is removed, and a voltage-controlled oscillator buffer that adjusts a slew rate of the clock output by the voltage-controlled oscillator according to the up signal and the down signal directly received from the phase detector and transmits the clock to the phase detector.
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公开(公告)号：US20240105792A1
公开(公告)日：2024-03-28
申请号：US18477258
申请日：2023-09-28
Inventor： Jinyong Cai
IPC: H01L29/423 , H01L29/66
CPC classification number: H01L29/4236 , H01L29/66477
Abstract: A method for manufacturing a MOSFET includes: forming a first trench and a second trench; forming a first shield gate dielectric layer and a first shielding conductor at a lower part of the first trench and a second shield gate dielectric layer and a second shielding conductor at a lower part of the second trench; forming a first dielectric interlayer and a second dielectric interlayer; forming a first gate dielectric layer and a first gate conductor at an upper part of the first trench and a second gate dielectric layer and a second gate conductor at an upper part of the second trench; and forming a body region, a source region, and a contact region. A dielectric constant of the second gate dielectric layer located in the second trench is greater than that of the first gate dielectric layer located in the first trench.
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29.发明公开公开(公告)号：US20240079445A1
公开(公告)日：2024-03-07
申请号：US17903745
申请日：2022-09-06
Inventor： Jiakun Wang , Xiao Hongxiu
CPC classification number: H01L29/0634 , H01L29/66734 , H01L29/7813 , H01L29/8725
Abstract: A super-junction MOS device with an integrated TMBS structure and a manufacturing method thereof are provided. The super-junction MOS device includes a main body. The TMBS structure is connected in parallel between at least two cells of the main body.
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公开(公告)号：US20230335621A1
公开(公告)日：2023-10-19
申请号：US18299245
申请日：2023-04-12
Inventor： Jiakun Wang , Zhaoming Yao
CPC classification number: H01L29/66734 , H01L29/407 , H01L29/7813 , H01L29/401
Abstract: Disclosed is a method for manufacturing a trench-type MOSFET, which comprises: providing a semiconductor structure, forming a trench in the semiconductor structure; forming a side oxide layer and dielectric layer in the trench; forming a shielding conductor in the trench; removing the hard mask; performing wet etching to remove the side oxide layer and dielectric layer; depositing an oxide layer from above the trench; etching the oxide layer to make an upper surface of the oxide layer lower than that of the shielding conductor; forming a gate dielectric layer and a gate conductor on the oxide layer, wherein the gate dielectric layer is located on an upper-portion side wall of the trench and separates the gate conductor from the semiconductor structure. By improving gate poly morphology, figure of merit of the device is optimized.
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