公开(公告)号：US20050020056A1

公开(公告)日：2005-01-27

申请号：US10923587

申请日：2004-08-19

Applicant: Charles Dennison ,  Trung Doan

Inventor： Charles Dennison ,  Trung Doan

IPC: H01L21/768 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/44

CPC classification number: H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76829 ,  Y10S438/95 ,  Y10S438/97

Abstract: A process for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process including forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.

Abstract translation: 在集成电路和器件的制造中形成垂直触点的工艺。 该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。 该方法包括在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。 在形成多级金属集成电路期间可以重复上述过程。

公开(公告)号：US06438016B1

公开(公告)日：2002-08-20

申请号：US10027569

申请日：2001-10-19

Applicant: Brent Keeth ,  Charles Dennison

Inventor： Brent Keeth ,  Charles Dennison

IPC: G11C506

CPC classification number: G11C11/403 ,  G11C11/406 ,  Y10S257/907

Abstract: The present invention is directed to an integrated circuit device having a memory cell for storing a data and refresh circuitry for refreshing that data in the memory cell. In one illustrative embodiment, the device comprises a memory cell having a storage element, a read/write access device, and a refresh access device. A read/write digit line is coupled to the read/write access device, and a refresh digit line is coupled to the refresh access device. A sense amplifier is coupled to the read/write digit line, and input/output circuitry is coupled to the read/write digit line. A refresh sense amplifier is coupled to the refresh digit line. The memory cell is constructed in such a way as to provide a large charge storage capacity in a relatively small, compact area.

Abstract translation: 本发明涉及具有用于存储数据的存储单元的集成电路装置和用于刷新存储单元中的数据的刷新电路。 在一个说明性实施例中，该设备包括具有存储元件，读/写访问设备和刷新访问设备的存储单元。 读/写数字线耦合到读/写访问设备，并且刷新数字线耦合到刷新访问设备。 读出放大器耦合到读/写数字线，并且输入/输出电路耦合到读/写数字线。 刷新读出放大器耦合到刷新数字线。 存储单元被构造成在相对较小，紧凑的区域中提供大的电荷存储容量。

公开(公告)号：US6159813A

公开(公告)日：2000-12-12

申请号：US819172

申请日：1997-03-17

Applicant: Aftab Ahmad ,  Charles Dennison

Inventor： Aftab Ahmad ,  Charles Dennison

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L21/84

CPC classification number: H01L29/6659 ,  H01L21/28247 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/7833 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S257/917 ,  H01L2924/00

Abstract: A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N- LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.

公开(公告)号：US5605857A

公开(公告)日：1997-02-25

申请号：US394546

申请日：1995-02-22

Applicant: Mark Jost ,  Charles Dennison

Inventor： Mark Jost ,  Charles Dennison

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L21/768 ,  H01L21/76877 ,  H01L27/10808 ,  H01L28/40 ,  H01L28/60 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90 ,  Y10S148/05

Abstract: A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; the capacitor comprising an inner storage node, a capacitor dielectric layer, and an outer cell node; the inner storage node electrically connecting with the one active area, the inner storage node having an upper surface at an elevation; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the other active area; and g) an electrically conductive bit line plug extending through the insulating layer to contact with the other active area and electrically interconnect the bit line with the other active area, the bit line plug being homogeneous in composition between the other active area and the elevation of the inner storage node upper surface. A method of producing such a construction is also disclosed.

Abstract translation: 半导体存储器件包括：a）半导体衬底; b）位于半导体衬底外侧的场效应晶体管栅极; c）在栅极的相对侧上形成在半导体衬底内的相对的有源区; d）与有源区域之一电连接的电容器; 所述电容器包括内部存储节点，电容器介电层和外部单元节点; 所述内部存储节点与所述一个活动区域电连接，所述内部存储节点具有在高度处的上表面; e）有点线 f）位于所述位线和所述另一有效区域之间的介电绝缘层; 并且g）导电位线插头，其延伸穿过所述绝缘层以与所述另一有源区域接触并且将所述位线与所述另一个有源区域电互连，所述位线插头在所述另一个有效区域和 内部存储节点上表面。 还公开了一种制造这种结构的方法。

公开(公告)号：US5250457A

公开(公告)日：1993-10-05

申请号：US838549

申请日：1992-02-19

Applicant: Charles Dennison

Inventor： Charles Dennison

IPC: H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L27/10852 ,  H01L21/76801 ,  H01L21/76829 ,  H01L27/10808

Abstract: A method of forming a buried bit line array of memory cells comprises: a) providing an array of word lines atop a semiconductor wafer; b) providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; c) providing a layer of first material (preferably polyimide) atop the wafer to a selected thickness; d) patterning and etching the layer of first material to define a pattern of buried bit line grooves for formation of buried bit lines therewithin, the bit line grooves having a first selected width; e) providing a layer of insulating material to a selected thickness atop the wafer over the patterned and etched layer of first material, the selected thickness of insulating material being less than half the first selected width, the layer of insulating material narrowing the bit line grooves to a smaller second width; f) providing bit line contact openings to second active regions within and at the bases of the second width bit line grooves; g) conductively doped polysilicon and on overlying higher conductive material are provided within the grooves for bit line formation; h) an array of capacitors are provided atop the wafer which electrically engage with first active regions.

Abstract translation: 形成存储单元的掩埋位线阵列的方法包括：a）在半导体晶片的顶部提供字线阵列; b）提供关于字线的有源区域以限定存储单元FET的阵列，所述有源区域由用于与存储单元电容器电连接的第一有源区域和用于与位线电连接的第二有源区域限定; c）在晶片顶上提供一层第一材料（优选聚酰亚胺）至所选择的厚度; d）图案化和蚀刻第一材料层以限定用于在其中形成掩埋位线的掩埋位线槽的图案，所述位线槽具有第一选定宽度; e）在所述图案化和蚀刻的第一材料层上的所述晶片的顶部上提供绝缘材料层，所述绝缘材料的所选厚度小于所述第一选定宽度的一半，所述绝缘材料层使所述位线沟槽变窄 到较小的第二宽度; f）向位于第二宽度位线槽的底部内和底部的第二有源区提供位线接触开口; g）导电掺杂的多晶硅和覆盖的较高导电材料设置在用于位线形成的凹槽内; h）在与第一有源区电接合的晶片顶上提供一组电容器。

公开(公告)号：US5206183A

公开(公告)日：1993-04-27

申请号：US838537

申请日：1992-02-19

Applicant: Charles Dennison

Inventor： Charles Dennison

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8242

CPC classification number: H01L27/10852 ,  H01L21/76885 ,  H01L21/76889 ,  H01L28/40

Abstract: A method of forming a bit line over capacitor array of memory cells includes providing a first layer of polyimide over word lines. Such layer is then patterned and etched to define storage node circuits. A first layer of conductively doped polysilicon is applied over the first layer of polyimide. A second layer of polyimide is applied over the first layer of conductively doped polysilicon. The second layer of polyimide and first layer of polysilicon are etched over the first layer of polyimide to define isolated cell storage nodes. Such can be conducted without any prior patterning or masking of the second layer of polyimide and first layer of polysilicon. A third layer of polyimide is provided atop the wafer over the isolated cell storage nodes. The third and first layers of polyimide are etched to define bit line contacts. Insulating spacers are provided about the periphery within the bit line contacts. Conductive material is deposited to provide conductive material pillars within the bit line contacts. Remaining portions of the first, second and third layers of polyimide are etched from the wafer. A capacitor cell dielectric layer is provided atop the individual storage nodes. A capacitor cell polysilicon layer is provided atop the capacitor cell dielectric layer to define an array of memory cell capacitors. An insulating layer is provided atop the cell polysilicon later. An array of digit lines are provided atop the wafer which electrically connect with the conductive material pillars elevationally above the cell capacitors.

Abstract translation: 在存储器单元的电容器阵列上形成位线的方法包括在字线上提供第一层聚酰亚胺。 然后对该层进行图案化和蚀刻以定义存储节点电路。 在第一层聚酰亚胺上施加第一层导电掺杂多晶硅。 在第一层导电掺杂多晶硅上施加第二层聚酰亚胺。 在第一层聚酰亚胺上蚀刻第二层聚酰亚胺和第一层多晶硅以限定隔离的电池存储节点。 这样可以不进行第二层聚酰亚胺和第一多晶硅层的任何先前的图案化或掩蔽来进行。 在隔离的电池存储节点上的晶片顶部提供第三层聚酰亚胺。 蚀刻第三层和第一层聚酰亚胺以限定位线接触。 围绕位线接触件周围的绝缘垫片设置。 导电材料被沉积以在位线触点内提供导电材料柱。 从晶片上蚀刻第一层，第二层和第三层聚酰亚胺的剩余部分。 电容器单元电介质层设置在各个存储节点的顶部。 电容器单元多晶硅层设置在电容器电介质层顶部以限定存储单元电容器阵列。 之后在单元多晶硅顶上提供绝缘层。 在晶片顶部提供数字线阵列，其电连接到电池电容器正上方的导电材料柱。

公开(公告)号：US20080116444A1

公开(公告)日：2008-05-22

申请号：US11998899

申请日：2007-12-03

Applicant: Charles Dennison

Inventor： Charles Dennison

IPC: H01L47/00

CPC classification number: G11C13/0004 ,  G11C13/0069 ,  G11C2013/0083 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144

Abstract: A thin film phase change memory may be provided with a layer which changes between amorphous and crystalline states. The threshold voltage of that layer may be increased in a variety of fashions. As a result of the threshold increase, it is possible to transition cells, initially fabricated in the set or low resistance state, into the reset or high resistance state. In one advantageous embodiment, after such initialization and programming, the threshold voltage increase is eliminated so that the cells operate thereafter without the added threshold voltage.

Abstract translation: 薄膜相变存储器可以设置有在非晶态和晶态之间变化的层。 该层的阈值电压可以以各种方式增加。 作为门限增加的结果，可以将初始以设定或低电阻状态制造的电池转换成复位或高电阻状态。 在一个有利的实施例中，在这样的初始化和编程之后，消除阈值电压增加，使得在没有增加的阈值电压的情况下，电池工作。

公开(公告)号：US07348620B2

公开(公告)日：2008-03-25

申请号：US11706000

申请日：2007-02-13

Applicant: Chien Chiang ,  Charles Dennison ,  Tyler Lowrey

Inventor： Chien Chiang ,  Charles Dennison ,  Tyler Lowrey

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L3/113

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

Abstract: Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the phase changes. The heater may be coupled to an appropriate conductor.

Abstract translation: 在一些情况下，通过将相变材料层形成为平面构型，相变存储器可以表现出改善的性能和较低的成本。 可以在相变材料层的下方设置加热器，以适当地加热材料以引起相变。 加热器可以耦合到适当的导体。

公开(公告)号：US20070281487A1

公开(公告)日：2007-12-06

申请号：US11841906

申请日：2007-08-20

Applicant: Charles Dennison ,  Trung Doan

Inventor： Charles Dennison ,  Trung Doan

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76829 ,  Y10S438/95 ,  Y10S438/97

Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.

Abstract translation: 在集成电路和器件的制造中提供用于形成垂直触点的工艺。 该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。 该方法包括在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。 在形成多级金属集成电路期间可以重复上述过程。

公开(公告)号：US20070158698A1

公开(公告)日：2007-07-12

申请号：US11612962

申请日：2006-12-19

Applicant: Charles Dennison ,  John Peters

Inventor： Charles Dennison ,  John Peters

IPC: H01L29/768

CPC classification number: H01L45/04 ,  H01L27/2427 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/1675

Abstract: In a phase change memory including an ovonic threshold switch, conduction around the phase change material layer in the ovonic threshold switch is reduced. In one embodiment, the reduction is achieved by undercutting the conductive layers on either side of the phase change material layer. In another embodiment, an angled ion implantation is carried out which damages the edge regions of the conductive layers that sandwich the phase change material layer.

Abstract translation: 在包括超声阈值开关的相变存储器中，减少了在超声波阈值开关中的相变材料层周围的传导。 在一个实施例中，通过在相变材料层的任一侧上切割导电层来实现所述还原。 在另一个实施例中，进行成角度的离子注入，其损害夹着相变材料层的导电层的边缘区域。