公开(公告)号：US5705838A

公开(公告)日：1998-01-06

申请号：US692748

申请日：1996-08-06

Applicant: Mark Jost ,  Charles Dennison

Inventor： Mark Jost ,  Charles Dennison

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/41

CPC classification number: H01L27/10852 ,  H01L21/768 ,  H01L21/76877 ,  H01L27/10808 ,  H01L28/40 ,  H01L28/60 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90 ,  Y10S148/05

Abstract: A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; the capacitor comprising an inner storage node, a capacitor dielectric layer, and an outer cell node; the inner storage node electrically connecting with the one active area, the inner storage node having an upper surface at an elevation; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the other active area; and g) an electrically conductive bit line plug extending through the insulating layer to contact with the other active area and electrically interconnect the bit line with the other active area, the bit line plug being homogeneous in composition between the other active area and the elevation of the inner storage node upper surface. A method of producing such a construction is also disclosed.

Abstract translation: 半导体存储器件包括：a）半导体衬底; b）位于半导体衬底外侧的场效应晶体管栅极; c）在栅极的相对侧上形成在半导体衬底内的相对的有源区; d）与有源区域之一电连接的电容器; 所述电容器包括内部存储节点，电容器介电层和外部单元节点; 所述内部存储节点与所述一个活动区域电连接，所述内部存储节点具有在高度处的上表面; e）有点线 f）位于位线和另一个有效区域之间的介电绝缘层; 并且g）导电位线插头，其延伸穿过所述绝缘层以与所述另一有源区域接触并且将所述位线与所述另一个有源区域电互连，所述位线插头在所述另一个有效区域和 内部存储节点上表面。 还公开了一种制造这种结构的方法。

公开(公告)号：US5900660A

公开(公告)日：1999-05-04

申请号：US916863

申请日：1997-08-22

Applicant: Mark Jost ,  Charles Dennison

Inventor： Mark Jost ,  Charles Dennison

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L21/768 ,  H01L21/76877 ,  H01L27/10808 ,  H01L28/40 ,  H01L28/60 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90 ,  Y10S148/05

Abstract: A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; the capacitor comprising an inner storage node, a capacitor dielectric layer, and an outer cell node; the inner storage node electrically connecting with the one active area, the inner storage node having an upper surface at an elevation; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the other active area; and g) an electrically conductive bit line plug extending through the insulating layer to contact with the other active area and electrically interconnect the bit line with the other active area, the bit line plug being homogeneous in composition between the other active area and the elevation of the inner storage node upper surface. A method of producing such a construction is also disclosed.

公开(公告)号：US5702990A

公开(公告)日：1997-12-30

申请号：US712616

申请日：1996-09-13

Applicant: Mark Jost ,  Charles Dennison

Inventor： Mark Jost ,  Charles Dennison

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/4763

CPC classification number: H01L27/10852 ,  H01L21/768 ,  H01L21/76877 ,  H01L27/10808 ,  H01L28/40 ,  H01L28/60 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90 ,  Y10S148/05

Abstract: A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; the capacitor comprising an inner storage node, a capacitor dielectric layer, and an outer cell node; the inner storage node electrically connecting with the one active area, the inner storage node having an upper surface at an elevation; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the other active area; and g) an electrically conductive bit line plug extending through the insulating layer to contact with the other active area and electrically interconnect the bit line with the other active area, the bit line plug being homogeneous in composition between the other active area and the elevation of the inner storage node upper surface. A method of producing such a construction is also disclosed.

公开(公告)号：US6110774A

公开(公告)日：2000-08-29

申请号：US920621

申请日：1997-08-27

Applicant: Mark Jost ,  Charles Dennison

Inventor： Mark Jost ,  Charles Dennison

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L21/768 ,  H01L21/76877 ,  H01L27/10808 ,  H01L28/40 ,  H01L28/60 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90 ,  Y10S148/05

Abstract: A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; the capacitor comprising an inner storage node, a capacitor dielectric layer, and an outer cell node; the inner storage node electrically connecting with the one active area, the inner storage node having an upper surface at an elevation; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the other active area; and g) an electrically conductive bit line plug extending through the insulating layer to contact with the other active area and electrically interconnect the bit line with the other active area, the bit line plug being homogeneous in composition between the other active area and the elevation of the inner storage node upper surface. A method of producing such a construction is also disclosed.

Abstract translation: 半导体存储器件包括：a）半导体衬底; b）位于半导体衬底外侧的场效应晶体管栅极; c）在栅极的相对侧上形成在半导体衬底内的相对的有源区; d）与有源区域之一电连接的电容器; 所述电容器包括内部存储节点，电容器介电层和外部单元节点; 所述内部存储节点与所述一个活动区域电连接，所述内部存储节点具有在高度处的上表面; e）有点线 f）位于位线和另一个有效区域之间的介电绝缘层; 并且g）导电位线插头，其延伸穿过所述绝缘层以与所述另一有源区域接触并且将所述位线与所述另一个有源区域电互连，所述位线插头在所述另一个有效区域和 内部存储节点上表面。 还公开了一种制造这种结构的方法。

公开(公告)号：US5605857A

公开(公告)日：1997-02-25

申请号：US394546

申请日：1995-02-22

Applicant: Mark Jost ,  Charles Dennison

Inventor： Mark Jost ,  Charles Dennison

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L21/768 ,  H01L21/76877 ,  H01L27/10808 ,  H01L28/40 ,  H01L28/60 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90 ,  Y10S148/05

Abstract: A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; the capacitor comprising an inner storage node, a capacitor dielectric layer, and an outer cell node; the inner storage node electrically connecting with the one active area, the inner storage node having an upper surface at an elevation; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the other active area; and g) an electrically conductive bit line plug extending through the insulating layer to contact with the other active area and electrically interconnect the bit line with the other active area, the bit line plug being homogeneous in composition between the other active area and the elevation of the inner storage node upper surface. A method of producing such a construction is also disclosed.

Abstract translation: 半导体存储器件包括：a）半导体衬底; b）位于半导体衬底外侧的场效应晶体管栅极; c）在栅极的相对侧上形成在半导体衬底内的相对的有源区; d）与有源区域之一电连接的电容器; 所述电容器包括内部存储节点，电容器介电层和外部单元节点; 所述内部存储节点与所述一个活动区域电连接，所述内部存储节点具有在高度处的上表面; e）有点线 f）位于所述位线和所述另一有效区域之间的介电绝缘层; 并且g）导电位线插头，其延伸穿过所述绝缘层以与所述另一有源区域接触并且将所述位线与所述另一个有源区域电互连，所述位线插头在所述另一个有效区域和 内部存储节点上表面。 还公开了一种制造这种结构的方法。

公开(公告)号：US20100283029A1

公开(公告)日：2010-11-11

申请号：US12454002

申请日：2009-05-11

Applicant: Charles Dennison ,  Wolodymyr Czubatyj ,  Jeff Fournier ,  Tom Latowski ,  James Reed ,  Regino Sandoval

Inventor： Charles Dennison ,  Wolodymyr Czubatyj ,  Jeff Fournier ,  Tom Latowski ,  James Reed ,  Regino Sandoval

IPC: H01L45/00 ,  H01L21/06 ,  H01L21/20

CPC classification number: H01L45/1233 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

Abstract: A memory includes multiple layers of deposited memory material. An etch is performed on at least one layer of deposited memory material prior to the deposition of a subsequent layer of memory material.

Abstract translation: 存储器包括多层沉积的存储器材料。 在沉积后续存储材料层之前，在至少一层沉积的存储材料上进行蚀刻。

公开(公告)号：US20080064200A1

公开(公告)日：2008-03-13

申请号：US11983188

申请日：2007-11-07

Applicant: Brian Johnson ,  Charles Dennison

Inventor： Brian Johnson ,  Charles Dennison

IPC: H01L21/44

CPC classification number: G06F21/125 ,  G06F21/10 ,  H01L45/06 ,  H01L45/122 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1666

Abstract: Briefly, in accordance with an embodiment of the invention, a method to manufacture a phase change memory is provided. The method may include forming a first electrode contacting the sidewall surface and the bottom surface of the phase change material. The method may further include forming a second electrode contacting the top surface of the phase change material.

Abstract translation: 简而言之，根据本发明的实施例，提供了制造相变存储器的方法。 该方法可以包括形成接触相变材料的侧壁表面和底表面的第一电极。 该方法还可以包括形成接触相变材料的顶表面的第二电极。

公开(公告)号：US20080020508A1

公开(公告)日：2008-01-24

申请号：US11904557

申请日：2007-09-27

Applicant: Charles Dennison

Inventor： Charles Dennison

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2427 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/1675

Abstract: A phase change memory may be formed in a way which reduces oxygen infiltration through a chalcogenide layer overlying a lower electrode. Such infiltration may cause oxidation of the lower electrode which adversely affects performance. In one such embodiment, an etch through an overlying upper electrode layer may be stopped before reaching a layer which overlies said chalcogenide layer. Then, photoresist used for such etching may be utilized in a high temperature oxygen plasma. Only after such plasma treatment has been completed is that overlying layer removed, which ultimately exposes the chalcogenide.

Abstract translation: 相变存储器可以以减少氧气穿过覆盖在下电极上的硫属化物层的方式形成。 这种渗透可能导致下部电极的氧化，这对性能有不利影响。 在一个这样的实施例中，通过覆盖的上电极层的蚀刻可以在到达覆盖所述硫族化物层的层之前停止。 然后，可以在高温氧等离子体中使用用于这种蚀刻的光致抗蚀剂。 只有在这样的等离子体处理完成之后，去除了上层，最终暴露了硫族化物。

公开(公告)号：US20070138467A1

公开(公告)日：2007-06-21

申请号：US11706000

申请日：2007-02-13

Applicant: Chien Chiang ,  Charles Dennison ,  Tyler Lowrey

Inventor： Chien Chiang ,  Charles Dennison ,  Tyler Lowrey

IPC: H01L31/00

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

Abstract: Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the phase changes. The heater may be coupled to an appropriate conductor.

Abstract translation: 在一些情况下，通过将相变材料层形成为平面构型，相变存储器可以表现出改善的性能和较低的成本。 可以在相变材料层的下方设置加热器，以适当地加热材料以引起相变。 加热器可以耦合到适当的导体。

公开(公告)号：US20060234469A1

公开(公告)日：2006-10-19

申请号：US11409134

申请日：2006-04-21

Applicant: David Dickerson ,  Richard Lane ,  Charles Dennison ,  Kunal Parekh ,  Mark Fischer ,  John Zahurak

Inventor： David Dickerson ,  Richard Lane ,  Charles Dennison ,  Kunal Parekh ,  Mark Fischer ,  John Zahurak

IPC: H01L21/76

CPC classification number: H01L21/76232 ,  H01L21/0332 ,  H01L21/76235

Abstract: In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.

Abstract translation: 一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物层和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。 另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。