公开(公告)号：US20250167166A1

公开(公告)日：2025-05-22

申请号：US19027974

申请日：2025-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junga LEE ,  Youngja Kim ,  Hyunki Kim ,  Youngmin Lee

IPC: H01L23/00 ,  B23K1/00 ,  B23K1/015 ,  B23K3/047 ,  B23K3/08 ,  B23K101/40

Abstract: An apparatus includes: a vapor generating chamber configured to accommodate a heat transfer fluid and to be filled with saturated vapor generated by the heat transfer fluid; a heater configured to heat the heat transfer fluid in the vapor generating chamber; a substrate stage configured to be movable upward or downward in the vapor generating chamber and to support a substrate on which an electronic device is mounted via a solder. The apparatus also includes at least one mesh plate extending in a horizontal direction in the vapor generating chamber. The at least one mesh plate includes a plurality of openings through which the vapor moves.

公开(公告)号：US20250167137A1

公开(公告)日：2025-05-22

申请号：US19027551

申请日：2025-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon KO ,  Un-Byoung KANG ,  Jaekyung YOO ,  Teak Hoon LEE

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

公开(公告)号：US20250167113A1

公开(公告)日：2025-05-22

申请号：US18754295

申请日：2024-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeewoong KIM ,  Jinkyu KIM ,  Yunsuk NAM ,  Yoonbeom PARK ,  Keunhwi CHO

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is an integrated circuit device including first and second power lines each overlapping a first cell region, an inter-cell separation region, and a second cell region on a substrate in a vertical direction to the substrate, a first power tap cell penetrating through the substrate and receiving a first voltage from the first power line, a second power tap cell penetrating through the substrate and receiving, from the second power line, a second voltage different from the first voltage, and a dummy gate insulating bridge including first and second dummy gate insulating lines, which are apart from each other with the first and second power tap cells therebetween, and defining a vacuum space, and connected to the first and second dummy gate insulating lines.

公开(公告)号：US20250167111A1

公开(公告)日：2025-05-22

申请号：US18674263

申请日：2024-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisoo OH ,  Kiil Kim ,  Changbea Park

IPC: H01L23/528 ,  H01L21/768

Abstract: Provided is a semiconductor device including a lower structure, a dielectric layer on the lower structure, and first and second interconnection lines extending in a first direction in the dielectric layer and alternately disposed and spaced apart from each other in a second direction, perpendicular to the first direction, at least one of the first interconnection lines includes a first subpattern and a second subpattern overlapping in the first direction and spaced apart from each other, at least one of the second interconnection lines includes a third subpattern and a fourth subpattern overlapping in the first direction and spaced apart from each other, two ends of the first subpattern and the second subpattern respectively facing each other in the first direction have a convex protruding shape, and two ends of the third subpattern and the fourth subpattern respectively facing each other in the first direction have a concave protruding shape.

公开(公告)号：US20250167106A1

公开(公告)日：2025-05-22

申请号：US18738802

申请日：2024-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemyung CHOI ,  Kang-ill SEO

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Provided is a semiconductor device which includes: a base layer including at least one transistor structure; and an interconnect structure above the base layer in a 3rd direction, wherein the interconnect structure includes a 1st metal line, a 2nd metal line, and at least one another metal line extended in a 1st direction and arranged at a 2nd direction, wherein at least a 1st portion of the 1st metal line having a 1st metal-to-metal distance to at least a portion of another metal line adjacent thereto in the 2nd direction has a greater height than at least a 1st portion of the 2nd metal line having a 2nd metal-to-metal distance to at least a portion of another metal line adjacent thereto in the 2nd direction, wherein the 1st metal-to-metal distance is greater than the 2nd metal-to-metal distance, and wherein the 1st direction and the 2nd direction horizontally intersect each other, and vertically intersect the 3rd direction.

公开(公告)号：US20250167093A1

公开(公告)日：2025-05-22

申请号：US18794303

申请日：2024-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： DOHOON KIM

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes: a package substrate including an insulating layer and a plurality of conductive patterns within the insulating layer and respectively including a wiring portion and a via portion; a semiconductor chip on the package substrate and connected to the plurality of conductive patterns; and a molding member that covers the package substrate and the semiconductor chip. The semiconductor chip is closer to a second edge than to an opposite first edge of the package substrate, the plurality of conductive patterns includes a first conductive pattern overlapping a first side surface of the semiconductor chip in a vertical direction and a second conductive pattern overlapping a second side surface of the semiconductor chip in a vertical direction, and a thickness in the vertical direction of a wiring portion of the first conductive pattern is different from a thickness of a wiring portion of the second conductive pattern.

公开(公告)号：US20250167064A1

公开(公告)日：2025-05-22

申请号：US18893952

申请日：2024-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Radwanul Hasan SIDDIQUE ,  Yibing Michelle WANG ,  Haeri Park HANANIA ,  Shailabh KUMAR

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/373 ,  H01L23/48

Abstract: Methods, systems and devices are disclosed including a substrate, a computational device mounted on the substrate, with a first surface of the substrate having one or more nanoelements formed within, the one or more nanoelements having a diameter of 100 nm-5,000 nm. In some embodiments, a heat dissipator may be mounted on the substrate, the heat dissipator having at least one nanostructure, and the one or more nanoelements forming a thermal conductive pathway between the computational device and the heat dissipator.

公开(公告)号：US20250167051A1

公开(公告)日：2025-05-22

申请号：US18765917

申请日：2024-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghyeon Hwang ,  Euijong Whang ,  Hyunsoo Kwak ,  Sung Yoon Ryu ,  Sooseok Lee ,  Younghoon Sohn

IPC: H01L21/66 ,  H01J37/28

Abstract: A method of operating an electronic device includes selecting, by at least one processor, M first sample-label pairs (M being a positive integer); obtaining, by the at least one processor, M K-values; selecting, by the at least one processor, M second sample-label pairs respectively corresponding to the M first sample-label pairs based on the M K-values, generating, by the at least one processor, M third sample-label pairs based on the M first sample-label pairs and the M second sample-label pairs, and training, by the at least one processor, a regression analysis module based on the M third sample-label pairs, and the regression analysis module is trained to predict labels, which are associated with the semiconductor device, from the M third sample-label pairs.

公开(公告)号：US20250166721A1

公开(公告)日：2025-05-22

申请号：US18761985

申请日：2024-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongha PARK ,  Seaeun Park ,  Saeeun Kim

IPC: G11C29/32 ,  G06F11/22

Abstract: A nonvolatile memory device includes at least one first universal interface bus (UIB) circuit coupled to a plurality of input/output (I/O) pads, at least one second UIB circuit coupled to the plurality of I/O pads, a core block including a first input terminal coupled to another block, and a plurality of second input terminals coupled to a first output terminal of the at least one first UIB circuit and a second output terminal of the at least one second UIB circuit, and at least one block configured to activate the at least one second UIB circuit.

公开(公告)号：US20250166677A1

公开(公告)日：2025-05-22

申请号：US18785979

申请日：2024-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jichull Jeong ,  Youngwoo Park ,  Seungjin Park ,  Jindo Byun ,  Seunghoon Lee ,  Eunsang Lee ,  Chaekang Lim

IPC: G11C7/14 ,  G11C7/06 ,  G11C7/10

Abstract: Disclosed is a memory device which includes a driver unit that includes a pull-up driver and a pull-down driver, a ZQ calibration unit that performs ZQ calibration with respect to the driver unit based on an external resistor and a first reference voltage and generates a first ZQ code corresponding to the first reference voltage, and a code conversion unit that generates a second ZQ code corresponding to a second reference voltage different from the first reference voltage, based on the first ZQ code.