公开(公告)号：US20190157147A1

公开(公告)日：2019-05-23

申请号：US16237948

申请日：2019-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo MYUNG ,  GeumJung SEONG ,  Jisoo OH ,  JinWook LEE ,  Dohyoung KIM ,  Yong-Ho JEON

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.

公开(公告)号：US20180061958A1

公开(公告)日：2018-03-01

申请号：US15794107

申请日：2017-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo MYUNG ,  GeumJung SEONG ,  Jisoo OH ,  JinWook LEE ,  Dohyoung KIM ,  Yong-Ho JEON

IPC: H01L29/49 ,  H01L21/768 ,  H01L29/66 ,  H01L23/535 ,  H01L29/161 ,  H01L29/16 ,  H01L29/06 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.

公开(公告)号：US20250167111A1

公开(公告)日：2025-05-22

申请号：US18674263

申请日：2024-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisoo OH ,  Kiil Kim ,  Changbea Park

IPC: H01L23/528 ,  H01L21/768

Abstract: Provided is a semiconductor device including a lower structure, a dielectric layer on the lower structure, and first and second interconnection lines extending in a first direction in the dielectric layer and alternately disposed and spaced apart from each other in a second direction, perpendicular to the first direction, at least one of the first interconnection lines includes a first subpattern and a second subpattern overlapping in the first direction and spaced apart from each other, at least one of the second interconnection lines includes a third subpattern and a fourth subpattern overlapping in the first direction and spaced apart from each other, two ends of the first subpattern and the second subpattern respectively facing each other in the first direction have a convex protruding shape, and two ends of the third subpattern and the fourth subpattern respectively facing each other in the first direction have a concave protruding shape.

公开(公告)号：US20250070021A1

公开(公告)日：2025-02-27

申请号：US18587425

申请日：2024-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Il KIM ,  Jisoo OH

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a semiconductor device and method of manufacturing same. The semiconductor device includes: a transistor on a substrate; a first wiring layer on the transistor, the first wiring layer including a first wiring electrically connected to the transistor; and a second wiring layer on the first wiring layer, the second wiring layer including an interlayer insulating layer and a second wiring provided in the interlayer insulating layer, wherein the second wiring includes a line structure and a first via structure, wherein the first via structure vertically connects the line structure and the first wiring, wherein the first via structure includes: a first outer surface in contact with the interlayer insulating layer; and a second outer surface in contact with the interlayer insulating layer and facing a direction opposite from the first outer surface, wherein the first outer surface and the second outer surface are curved surfaces, and wherein a curvature of the first outer surface and a curvature of the second outer surface are different from each other.

公开(公告)号：US20170200802A1

公开(公告)日：2017-07-13

申请号：US15401562

申请日：2017-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwoo MYUNG ,  GeumJung SEONG ,  Jisoo OH ,  JinWook LEE ,  Dohyoung KIM ,  Yong-Ho JEON

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/16 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L27/088 ,  H01L29/161

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.