公开(公告)号：US20240098991A1

公开(公告)日：2024-03-21

申请号：US18520526

申请日：2023-11-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Toan Le ,  Nghia Le ,  Hien Pham

IPC: H10B41/42 ,  G06N3/08 ,  G11C16/04 ,  H01L29/788

CPC classification number: H10B41/42 ,  G06N3/08 ,  G11C16/0425 ,  H01L29/7883

Abstract: In one example, a system comprises an array comprising selected memory cells; an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register; wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift operations to generate an output indicating values stored in the selected memory cells.

公开(公告)号：US20240081056A1

公开(公告)日：2024-03-07

申请号：US18139347

申请日：2023-04-25

Applicant: Powerchip Semiconductor Manufacturing Corporation

Inventor： Yi-Yeh Chuang ,  Zih-Song Wang ,  Li-Ta Chen ,  Shun-Yu Gao

IPC: H10B41/42 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/42 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

Abstract: A double patterning method of manufacturing select gates and word lines is provided in the present invention, including forming first string patterns composed of word line patterns and select gate patterns on a target layer, forming a conformal spacer layer on first string patterns, wherein the spacer layer forms trenches between first string patterns, forming a fill layer filling up the trenches on the spacer layer, removing fill layer outside of the trenches, so that fill layer in the trenches forms second string patterns, wherein the second string patterns and the first string patterns are spaced apart, removing exposed spacer layer, so that the first string patterns and the second string patterns constitute target patterns spaced apart from each other on the target layer, and performing an etching process using those target patterns as a mask to remove exposed target layer, so as to form word lines and select gates.

公开(公告)号：US11877447B2

公开(公告)日：2024-01-16

申请号：US18297659

申请日：2023-04-10

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Hsiu-Han Liao ,  Che-Fu Chuang

IPC: H01L21/00 ,  H10B41/42 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30

CPC classification number: H10B41/42 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30

Abstract: Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.

公开(公告)号：US20230389319A1

公开(公告)日：2023-11-30

申请号：US18446579

申请日：2023-08-09

Applicant: Kioxia Corporation

Inventor： Masaki TSUJI ,  Yoshiaki FUKUZUMI

IPC: H10B43/27 ,  H01L29/66 ,  H01L29/792 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B41/42 ,  H10B43/10 ,  H10B43/20 ,  H10B51/20

CPC classification number: H10B43/27 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B41/42 ,  H10B43/10 ,  H10B43/20 ,  H10B51/20

Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.

公开(公告)号：US20230255026A1

公开(公告)日：2023-08-10

申请号：US18297659

申请日：2023-04-10

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Hsiu-Han Liao ,  Che-Fu Chuang

IPC: H10B41/42 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30

CPC classification number: H10B41/42 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30

Abstract: Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.

公开(公告)号：US11678484B2

公开(公告)日：2023-06-13

申请号：US17376079

申请日：2021-07-14

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Hsiu-Han Liao ,  Che-Fu Chuang

IPC: H01L21/00 ,  H10B41/42 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30

CPC classification number: H10B41/42 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30

Abstract: Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.

公开(公告)号：US20240381634A1

公开(公告)日：2024-11-14

申请号：US18470923

申请日：2023-09-20

Applicant: SK keyfoundry Inc.

Inventor： Yangbeom KANG ,  Seungmo JO ,  Gyeoungmin MIN

IPC: H10B41/30 ,  H10B41/42

Abstract: A semiconductor device manufacturing method includes forming a tunneling gate insulating layer and a floating gate Poly-Si layer in a substrate, an inter-poly dielectric layer on the floating gate Poly-Si layer, a control gate Poly-Si layer on the inter-poly dielectric layer, and a control gate hard mask layer on the control gate Poly-Si layer, performing a patterning process on the control gate hard mask layer, the control gate Poly-Si layer, the inter-poly dielectric layer, the floating gate Poly-Si layer and the tunneling gate insulating layer to form a gate stack, forming a select gate insulating layer on the gate stack, and a select gate disposed on the select gate insulating layer, performing a removing process on the select gate insulating layer and the control gate hard mask to expose a top surface of the control gate, and forming a silicide layer on the control gate.

公开(公告)号：US12021074B2

公开(公告)日：2024-06-25

申请号：US17516920

申请日：2021-11-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Roberto Simola

IPC: H01L29/40 ,  H01L21/70 ,  H01L27/01 ,  H10B41/41 ,  H10B41/42

CPC classification number: H01L27/016 ,  H01L21/707 ,  H10B41/41 ,  H10B41/42

Abstract: An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.

公开(公告)号：US20240107755A1

公开(公告)日：2024-03-28

申请号：US18534818

申请日：2023-12-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

IPC: H10B41/35 ,  G11C16/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/788 ,  H10B41/41 ,  H10B41/42

CPC classification number: H10B41/35 ,  G11C16/10 ,  H01L29/0649 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/41 ,  H10B41/42 ,  G11C16/30

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a first well region disposed within a substrate and comprising a first doping type. A conductive structure overlies the first well region. A pair of first doped regions is disposed within the first well region on opposing sides of the conductive structure. The pair of first doped regions comprise a second doping type opposite the first doping type. A pair of second doped regions is disposed within the first well region on the opposing sides of the conductive structure. The pair of second doped regions comprise the second doping type and are laterally offset from the pair of first doped regions by a non-zero distance.

公开(公告)号：US11943920B2

公开(公告)日：2024-03-26

申请号：US17468637

申请日：2021-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Xiaojuan Gao ,  Boon Keat Toh

IPC: H01L27/11531 ,  H01L21/28 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B41/42 ,  H10B43/40

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7881 ,  H01L29/792 ,  H10B43/40

Abstract: A semiconductor memory device includes a semiconductor substrate, a select gate on the semiconductor substrate, a control gate disposed adjacent to the select gate and having a first sidewall and a second sidewall, and a charge storage layer between the control gate and the semiconductor substrate. The control gate includes a third sidewall close to the second sidewall of the select gate, a fourth sidewall opposite to the third sidewall, and a non-planar top surface between the third sidewall and the fourth sidewall. The non-planar top surface includes a first surface region that descends from the third sidewall to the fourth sidewall. The charge storage layer extends to the second sidewall of the select gate.