公开(公告)号：US3879577A

公开(公告)日：1975-04-22

申请号：US39969573

申请日：1973-09-24

Applicant: LICENTIA GMBH

Inventor： PROGLER MAX

IPC: H04L1/16 ,  H04L1/18 ,  G08C25/00 ,  G06F11/00 ,  H04L1/10

CPC classification number: H04L1/1845 ,  H04L1/16 ,  H04L1/1809 ,  H04L1/1838 ,  H04L1/1874

Abstract: In a data transmission system in which blocks of binary data are transmitted over a transmission channel from a data source in a transmitter to a data user in a receiver, with each block being tested in the receiver and each incorrectly received block giving rise to an ''''error'''' receipt signal which is delivered to the transmitter over a return channel, retransmission of an incorrectly received block is effectuated by storing each transmitted block in the transmitter and delaying each received block in the receiver for a time equal to the period which elapses between transmission of a block and arrival at the transmitter of the receipt signal for that block, normally supplying each received block to the user after such delay, retransmitting each received block resulting in an error receipt signal upon arrival of such signal at the transmitter, and delivering each retransmitting block directly to the user without such delay if such retransmitted block does not give rise to another error receipt signal. Only those blocks which create an error receipt signal are retransmitted by the transmitter.

Abstract translation: 在其中二进制数据块通过传输信道从发射机中的数据源发送到接收机中的数据用户的数据传输系统中，其中每个块在接收机中被测试，并且每个错误接收的块产生“ 错误“接收信号，其通过返回信道传送到发射机，通过将发送的每个块存储在发射机中并将接收机中的每个接收的块延迟一段时间等于传输之间的时间来实现不正确接收的块的重传 并且到达该块的接收信号的发射机，通常在这样的延迟之后向用户提供每个接收到的块，重传每个接收到的块，从而在这种信号到达发射机时导致错误接收信号，并且传送每个 如果这样的重传块不会引起另一个错误r，则直接向用户重传块而没有这样的延迟 eceipt信号。 只有那些创建错误接收信号的块才被发送器重传。

公开(公告)号：US3781791A

公开(公告)日：1973-12-25

申请号：US3781791D

申请日：1971-12-13

Applicant: BELL TELEPHONE LABOR INC

Inventor： SULLIVAN D

IPC: H03M13/15 ,  H04L1/10 ,  G08C25/04 ,  H03K13/34

CPC classification number: H03M13/151

Abstract: Apparatus is disclosed for performing Berlekamp''s algorithm to effect the decoding of binary BCH codes. In particular, in accordance with the present invention, Berlekamp''s algorithm is restated such that two variables are advantageously combined and a simplified circuit disclosed for performing the iterations specified by the restated algorithm.

Abstract translation: 公开了用于执行Berlekamp算法来实现二进制BCH码的解码的装置。 特别地，根据本发明，重申了Berlekamp的算法，使得有利地组合两个变量，并且公开了用于执行由重新计算的算法指定的迭代的简化电路。

公开(公告)号：US3766521A

公开(公告)日：1973-10-16

申请号：US3766521D

申请日：1972-09-26

Applicant: IBM

Inventor： CARTER W ,  HSIEH E ,  WADIA A

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00 ,  H04L1/10 ,  G11C29/00

CPC classification number: G06F11/1028

Abstract: Novel error correction and detection codes and self-checking translators therefor are disclosed. A first of these codes is a t b-adjacent bit group error correcting and t+d b-adjacent dadjacent bit group error detecting code using a quantity of 2t+d groups of b check bits. This code with a b-bit BSM (basic storage module) memory organization is capable of correcting b-adjacent errors due to failures in any t basic storage modules, detecting b-adjacent errors due to failures in any t+d basic storage modules, and, because of the translator design, detecting with high probability b-adjacent errors in 2t+2d-1 storage modules where 1

Abstract translation: 公开了新的错误校正和检测代码及其自检翻译器。 这些代码中的第一个是使用bt个校验位的2t + d组的tb相邻位组纠错和t + d b相邻的d相邻位组检错码。 具有b位BSM（基本存储模块）存储器组织的代码能够校正由于任何t个基本存储模块中的故障导致的b相邻错误，检测由于任何t + d个基本存储模块中的故障导致的b相邻错误， 并且由于翻译器设计，在2t + 2d-1个存储模块中检测出具有高概率b相邻误差，其中1

公开(公告)号：US3609682A

公开(公告)日：1971-09-28

申请号：US3609682D

申请日：1969-07-16

Applicant: GEN ELECTRIC

Inventor： MITCHELL MICHAEL E

IPC: G06F11/00 ,  H03M13/45 ,  H04L1/00 ,  G08C25/00 ,  H04L1/10

CPC classification number: H04L1/0057 ,  H03M13/45 ,  H03M13/458

Abstract: An error correcting decoder circuit for decoding redundantly coded received digital signals. Estimator bits are generated from selected bits of a received code word, and estimator reliability signals are generated in accordance with word-bit error probability signals derived from the received analog signal amplitudes associated with the same selected bits of the code word as are used for generating the estimator bits. The estimator reliability signals are used as a basis for weighting the bipolar estimator bit voltages, by increasing or decreasing their absolute values, whereby the more reliable estimator bits are given greater weights at the input of a threshold decision circuit. The threshold decision circuit generates an output bit in accordance with the arithmetic sum of the weighted estimator bit voltages, except that it substitutes the appropriate received bit in place of the unreliable threshold decision that arises in the event that the sum is small in magnitude. Control circuitry is provided for causing repetitive shifting of the word bits in a first shift register and of word-bit error probability signals in a second shift register, for performing step-by-step decoding of a received word with the aid of the received signal reliability indications. The invention thus provides a means of augmenting the digital error correction capability of decoders through the use of auxiliary outputs from the receiver which indicate the received signal quality.

公开(公告)号：US3601800A

公开(公告)日：1971-08-24

申请号：US3601800D

申请日：1969-09-30

Applicant: IBM

Inventor： LEE HUA-TUNG

IPC: G06F11/10 ,  G06F12/16 ,  H03M13/00 ,  H04L1/00 ,  G08C25/00 ,  H04L1/10

CPC classification number: H04L1/0057

Abstract: Data signals are encoded in an (n,k) cyclic code and checked for errors and corrected. The encoding and correction decoding apparatus includes an n-k stage parallel input parallel feedback shift register adapted to process the data digit signals in groups of c digits where the number c is greater than n-k. An example of implementation is disclosed for the specific case: n 72, k 64, and c 18, illustrating that encoding and/or error check decoding are completed in only 4 ( n/c) parallel shifts and that error correction decoding is accomplished in a maximum of only 3 additional parallel shifts timed to coincide with the handling of the data signals.

公开(公告)号：US3548313A

公开(公告)日：1970-12-15

申请号：US3548313D

申请日：1968-04-05

Applicant: PHILIPS CORP

Inventor： GERWEN PETRUS JOSEPHUS VAN

IPC: H04L25/03 ,  H04L1/10

CPC classification number: H04L25/03133

公开(公告)号：US3534331A

公开(公告)日：1970-10-13

申请号：US3534331D

申请日：1967-08-15

Applicant: STANFORD RESEARCH INST

Inventor： KAUTZ WILLIAM H

IPC: H03M13/19 ,  H04L1/00 ,  G08C25/00 ,  H04L1/10

CPC classification number: H03M13/19

公开(公告)号：US3505643A

公开(公告)日：1970-04-07

申请号：US3505643D

申请日：1965-07-06

Applicant: TELETYPE CORP

Inventor： RESZKA ALFONS

IPC: H04L1/00 ,  H04L1/10

CPC classification number: H04L1/004

公开(公告)号：US3484745A

公开(公告)日：1969-12-16

申请号：US3484745D

申请日：1967-06-26

Applicant: SAGEM

Inventor： SOURGENS ROGER P

IPC: H04L1/00 ,  H04L1/18 ,  H04L1/10

CPC classification number: H04L1/00

公开(公告)号：US07860200B2

公开(公告)日：2010-12-28

申请号：US11871184

申请日：2007-10-12

Applicant: William N. Furman ,  John W. Nieto ,  Fred C. Kellerman ,  Brian C. Padalino

Inventor： William N. Furman ,  John W. Nieto ,  Fred C. Kellerman ,  Brian C. Padalino

IPC: H04L1/10

CPC classification number: H04B1/1027 ,  H04L25/03038

Abstract: A communications system receives a modulated signal that carries encoded communications data. An adaptive filter has an input, a plurality of non-adaptive and adaptive filter taps with weighted coefficients, and an output. The received signal is passed through the adaptive filter and around adaptive filter and a switch selects which signal to pass to demodulator based on measured output power of the adaptive filter and of the original received signal. A demodulator and decoder receive the filtered output signal and demodulate and decode the signal to obtain the communications data.

Abstract translation: 通信系统接收携带编码通信数据的调制信号。 自适应滤波器具有输入，具有加权系数的多个非自适应和自适应滤波器抽头以及输出。 接收的信号通过自适应滤波器并在自适应滤波器周围，开关根据自适应滤波器的测量输出功率和原始接收信号选择哪个信号传递给解调器。 解调器和解码器接收滤波后的输出信号并对信号进行解调和解码以获得通信数据。