公开(公告)号：US3766521A

公开(公告)日：1973-10-16

申请号：US3766521D

申请日：1972-09-26

Applicant: IBM

Inventor： CARTER W ,  HSIEH E ,  WADIA A

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00 ,  H04L1/10 ,  G11C29/00

CPC classification number: G06F11/1028

Abstract: Novel error correction and detection codes and self-checking translators therefor are disclosed. A first of these codes is a t b-adjacent bit group error correcting and t+d b-adjacent dadjacent bit group error detecting code using a quantity of 2t+d groups of b check bits. This code with a b-bit BSM (basic storage module) memory organization is capable of correcting b-adjacent errors due to failures in any t basic storage modules, detecting b-adjacent errors due to failures in any t+d basic storage modules, and, because of the translator design, detecting with high probability b-adjacent errors in 2t+2d-1 storage modules where 1

Abstract translation: 公开了新的错误校正和检测代码及其自检翻译器。 这些代码中的第一个是使用bt个校验位的2t + d组的tb相邻位组纠错和t + d b相邻的d相邻位组检错码。 具有b位BSM（基本存储模块）存储器组织的代码能够校正由于任何t个基本存储模块中的故障导致的b相邻错误，检测由于任何t + d个基本存储模块中的故障导致的b相邻错误， 并且由于翻译器设计，在2t + 2d-1个存储模块中检测出具有高概率b相邻误差，其中1

公开(公告)号：US3737870A

公开(公告)日：1973-06-05

申请号：US3737870D

申请日：1972-04-24

Applicant: IBM

Inventor： CARTER W ,  HSIEH E ,  WADIA A

IPC: G06F12/16 ,  G06F12/06 ,  G11C29/00 ,  G06F11/00 ,  G06F13/06

CPC classification number: G11C29/70

Abstract: There is disclosed a switching arrangement for effecting storage module reconfiguration in a data processing system wherein the memory comprises a quantity q of operating n-bit/BSM''s (basic storage modules) and a quantity s of spare n-bit/BSM''s. The arrangement comprises an input status register means which in turn comprises an input status register associated with each of the BSM''s respectively, which control an input reconfiguration network, and an output status register means which comprises an output status register respectively associated with each of the BSM''s, which control an output reconfiguration network. The input and output status registers and the input and output reconfiguration networks are of like structures, respectively. Initially, in normal operation, the operating BSM''s are connected to respective bit positions and all of the input and output status registers assume a chosen initial state. Initially, upon the ascertaining from a diagnosis, for example, that one of the operating BSM''s has failed, the input status register with which the failed BSM is associated is forced to a parity state opposite from the normal operating parity state, and all of the input status registers succedding in designated numerical value are switched to a next state. This causes the failed BSM to be disconnected from the input; the input originally connected to the failed BSM is connected to the BSM of succeeding higher value, the next higher input connected to the next BSM and so on until the last input is connected to the first pare BSM. At this point, all of the contents of the memory, i.e., the initially operating BSM''s, are passed through the output reconfiguration network under the control of the output status registers (which is not yet altered) and through a correction circuit wherein there is provided means for applying an error correction code. The memory contents are then passed from the correction circuit back into the present operating BSM''s through the input reconfiguration network under the control of the input status registers. Thereafter, the contents of the output status registers are then brought into conformity with the present contents of the input status registers whereupon normal operation can resume. The arrangement permits as many changes in the contents, i.e., states of the status registers after their initial states as there are spare BSMM''s in the memory organization, the contents of status registers of operating BSM''s which succeed a failed BSM being switched to a next state. Suitably, an operating parity state of a status register is of even parity and, when its associated BSM fails, its state is forced to an odd parity. An algorithm is presented for diagnosing as a failed BSM which is based upon the criterion of the ascertaining of a bit position which has undergone corrections most frequently over a chosen period of time. The switching arrangement also contemplates a basic storage module reconfiguration in the case of a status register failure in which situation, similar events ensue in the arrangements operation as would have occurred has a BSM failed.