公开(公告)号：US3737870A

公开(公告)日：1973-06-05

申请号：US3737870D

申请日：1972-04-24

Applicant: IBM

Inventor： CARTER W ,  HSIEH E ,  WADIA A

IPC: G06F12/16 ,  G06F12/06 ,  G11C29/00 ,  G06F11/00 ,  G06F13/06

CPC classification number: G11C29/70

Abstract: There is disclosed a switching arrangement for effecting storage module reconfiguration in a data processing system wherein the memory comprises a quantity q of operating n-bit/BSM''s (basic storage modules) and a quantity s of spare n-bit/BSM''s. The arrangement comprises an input status register means which in turn comprises an input status register associated with each of the BSM''s respectively, which control an input reconfiguration network, and an output status register means which comprises an output status register respectively associated with each of the BSM''s, which control an output reconfiguration network. The input and output status registers and the input and output reconfiguration networks are of like structures, respectively. Initially, in normal operation, the operating BSM''s are connected to respective bit positions and all of the input and output status registers assume a chosen initial state. Initially, upon the ascertaining from a diagnosis, for example, that one of the operating BSM''s has failed, the input status register with which the failed BSM is associated is forced to a parity state opposite from the normal operating parity state, and all of the input status registers succedding in designated numerical value are switched to a next state. This causes the failed BSM to be disconnected from the input; the input originally connected to the failed BSM is connected to the BSM of succeeding higher value, the next higher input connected to the next BSM and so on until the last input is connected to the first pare BSM. At this point, all of the contents of the memory, i.e., the initially operating BSM''s, are passed through the output reconfiguration network under the control of the output status registers (which is not yet altered) and through a correction circuit wherein there is provided means for applying an error correction code. The memory contents are then passed from the correction circuit back into the present operating BSM''s through the input reconfiguration network under the control of the input status registers. Thereafter, the contents of the output status registers are then brought into conformity with the present contents of the input status registers whereupon normal operation can resume. The arrangement permits as many changes in the contents, i.e., states of the status registers after their initial states as there are spare BSMM''s in the memory organization, the contents of status registers of operating BSM''s which succeed a failed BSM being switched to a next state. Suitably, an operating parity state of a status register is of even parity and, when its associated BSM fails, its state is forced to an odd parity. An algorithm is presented for diagnosing as a failed BSM which is based upon the criterion of the ascertaining of a bit position which has undergone corrections most frequently over a chosen period of time. The switching arrangement also contemplates a basic storage module reconfiguration in the case of a status register failure in which situation, similar events ensue in the arrangements operation as would have occurred has a BSM failed.

公开(公告)号：US3784977A

公开(公告)日：1974-01-08

申请号：US3784977D

申请日：1972-06-20

Applicant: IBM

Inventor： CARTER W ,  WADIA A

IPC: G01R31/28 ,  G06F11/08 ,  G06F11/16 ,  G06F11/22 ,  H03M13/00 ,  H04L1/24 ,  G06F11/12

CPC classification number: G06F11/085 ,  H03K19/0075

Abstract: There is disclosed a self-testing checking circuit which checks that greater than or equal to k out of n input variables are 1. This circuit has the output (1,0) or (0,1) if the > OR = k condition is satisfied and the output (0,0) or (1,1) if it is not. The circuit is self-testing, i.e., every line other than the primary inputs is tested during normal operation. The logical equation representing this circuit is (CK,N,DK,N) (AN.EK,N 1(A1,A2, . . . ,AN 1),AN.EK 1,N 1(A1,A2, . . . ,AN 1)) WHEREIN A1, . . . ,AN ARE THE N INPUT VARIABLES, EK,N,(A1,A2, . . . ,AN) DENOTES THE FUNCTION WITH THE THRESHOLD K, THE FUNCTION BEING 1 IF GREATER THAN OR EQUAL TO K OF THE N INPUT VARIABLES A1,A2, . . . ,AN ARE 1. It is suitably implemented as an OR circuit of (k) AND circuits, each of the latter AND circuits being a conjunct constituted by k of the n input variables. The function (ck,ndk,n) is a two-output threshold k function, i.e., it is (0,1) or (1,0) if greater than or equal to k out of the n input variable are 1 and (0,0) otherwise. Logical equations representing the two output k threshold function are CK,N ANA1A2 . . . AKVANA1A2 . . . AK 1AK 1V . . . VANAN K . . . AN 1 DK,N ANA1A2 . . . AK 1 V ANA1A2 . . . AK 2AK V . . . V ANAN K 1 . . . AN 1 WHEREIN V REPRESENTS THE OR function. A two-output self-testing circuit which checks for less than or equal to k out of n input variables equal to 1 is represented by the following logical equation (GK,N,HK,N) (ANVFN K,N 1(A1, . . . , AN 1), ANVFN K 1,N 1 (A1, . . . , AN 1)) WHEREIN (GK,N, HK,N) IS THE TWO OUTPUT THRESHOLD WHICH IS (0,1) OR (1,0) IF LESS THAN OR EQUAL TO K OUT OF N INPUT VARIABLES ARE 1, A1, . . . ,AN ARE THE INPUT VARIABLES, FK,N IS THE FUNCTION WITH THE THRESHOLD K, I.E., IT IS 0 IF GREATER THAN OR EQUAL TO K OUT OF N INPUTS ARE 0. The function fk,n is represented by the following equation FK,N (A V A2 V A2 V . . . V AK) (A1VA2V . . . VAK 1VAK 1) . . . (AN K 1V . . . VAN) WHICH COMPRISES (K) OR circuits providing inputs to an AND circuit, each OR circuit being constituted by a disjunct of k input variables. By providing the outputs of both of the twooutput circuits mentioned above to a morphic AND circuit, there is provided a circuit which indicates whether greater than or equal to i of the input variables and less than or equal to k of the input variables are 1. When this condition is obtained, the output of the morphic AND circuit is either (0,1) or (1,0).

Abstract translation: 公开了一种自检检查电路，其检查n个输入变量中大于或等于k个。该电路具有输出（1,0）或（0,1），如果> / = k条件是 满意和输出（0,0）或（1,1）如果不是。 该电路是自检的，即在正常操作期间测试除主输入之外的每一行。 表示该电路的逻辑方程为（CK，N，DK，N）=（AN.EK，N-1（A1，A2，...，A N-1），AN.E K-1，N-1 （A1，A2，...，A N-1））。 。 。 ，A是N输入变量，EK，N，（A1，A2，...，AN）用阈值K表示函数，如果大于或等于N个输入变量A1，A2的函数 ，。 。 。 ，A N ARE 1.它被适当地实现为（k）个AND电路的OR电路，后一个AND电路中的每一个是由n个输入变量的k构成的连接。 函数（ck，nd k，n）是双输出阈值k函数，即如果n个输入变量中的k大于等于1，则为（0,1）或（1,0） （0,0）否则。 表示两个输出k阈值函数的逻辑方程是CK，N = AN A1 A2。 。 。 AK VAN A1 A2。 。 。 AK-1 AK + 1 V。 。 。 万安科 。 。 AN-1 DK，N = AN A1 A2。 。 。 AK-1 V AN A1 A2。 。 。 AK-2 AK V。 。 。 V AN AN-K + 1。 。 。 AN-1 V代表OR功能。

公开(公告)号：US3780276A

公开(公告)日：1973-12-18

申请号：US3780276D

申请日：1972-06-20

Applicant: IBM

Inventor： CARTER W ,  WADIA A

IPC: G06F11/08 ,  G06F11/18 ,  G06F11/20 ,  G06F13/00 ,  G06F11/00

CPC classification number: G06F11/181 ,  G06F11/183

Abstract: The interface disclosed herein is capable of operating in the TMR/S (triple modular redundancy with sparing), the comparison, and the simplex modes. The interface controls the interconnection between m1 , . . . , mn identical sending modules and M1 , . . . , Mn identical receiving modules. To this end, there are provided 1, . . . , n control registers which comprise 1, . . . , n bits and an (n+1)th control register which comprises a single bit RS. The register bits are employed to provide n2 forcing functions for the outputs d1, . . . , dn of the sending modules which are represented by the following logical equation:

WHEREIN J IS THE BIT NUMBER, 1, . . . , N, I IS THE REGISTER NUMBER 1,..., N, THE SYMBOL N SIGNIFIES MODULO N AND V represents the OR function. The n2 forcing functions are respectively applied in sets of n viz., f1i, f2i, . . . , fni i 1,2, . . . , n to (1, . . . , n)th threshold function circuits, each of the latter circuits producing a ''''1'''' output when > OR = 2 of the inputs thereto are ''''1'''', the outputs of the (1, . . . , n)th threshold function circuits being applied to the M1, . . . , Mn)th receiving modules, respectively. From the register settings and the sending module outputs, there are generated pairs represented by the logical equation Cij (di V Rij V Rji V RS, djRijRji V Rs) for j i+1 (i 1, 3, 5, . . . , n-1) Cij (di V Rij V Rji, djRijRji) for j NOT = i+i WHEREIN THE IJ PAIR IN THE FIRST EQUATION CAN TAKE THE VALUES OF 13, 14, . . . , 1N, 24N, . . . , (N-2)N. From the pairs, (ij), there are generated register triggers having the following equations: A1 +/C12 Lambda M C13 M C14 Lambda M . . . Lambda M C1n A2 +/C21 Lambda M C23 Lambda M C24 Lambda M . . . Lambda M C2n An +/C1n Lambda M C2n Lambda M C3n Lambda M . . . Lambda M C(n 1)n WHEREIN THE SYMBOL Lambda M represents the morphic AND function called the RCCO in U.S. Pat. No. 3,559,167, the symbol + signifies the exclusive OR function on the pair of lines that are outputs of the morphic AND. The (A1, . . . ,An)th triggers are applied to the (1, . . . , n)th bits of the registers respectively, to switch the bits to the opposites of their initial binary states whereby, upon the generation of a register trigger Aj and the consequent switching of register bits R1j, . . . , Rnj to their opposite binary states, sending module mj is disconnected from operation. To operate the interface in the TMR/S mode, initially all of the bits of the (1, . . . , n)th registers are initially set to the 1 state and the bit of the (n+ 1)th register is set to the 0 state. To operate the interface in thE comparison mode, all the bits bearing the same numerical designation as the sending module which are to be compared in the registers bearing the same numerical designations as the sending modules which are to be compared are initially set to the 1 state with all of the other bits set to the 0 state. To operate in the simplex mode, all of the bits in the (1, . . . ,n)th registers except those bearing the same numerical designation as that borne by the register in which they are contained are set to the 0 state, the excepted bits being set to the 1 state. Also, in the simplex mode of operation, the bit of the n+1th register is set to the 1 state.

Abstract translation: 本文公开的接口能够以TMR / S（备用三重模块冗余），比较和单工模式进行操作。 接口控制m1之间的互连。 。 。 ，mn相同的发送模块和M1，。 。 。 ，Mn相同的接收模块。 为此，提供了1，。 。 。 ，n个控制寄存器，包括1，。 。 。 ，n位和第（n + 1）个控制寄存器，其包括单个

公开(公告)号：US3766521A

公开(公告)日：1973-10-16

申请号：US3766521D

申请日：1972-09-26

Applicant: IBM

Inventor： CARTER W ,  HSIEH E ,  WADIA A

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00 ,  H04L1/10 ,  G11C29/00

CPC classification number: G06F11/1028

Abstract: Novel error correction and detection codes and self-checking translators therefor are disclosed. A first of these codes is a t b-adjacent bit group error correcting and t+d b-adjacent dadjacent bit group error detecting code using a quantity of 2t+d groups of b check bits. This code with a b-bit BSM (basic storage module) memory organization is capable of correcting b-adjacent errors due to failures in any t basic storage modules, detecting b-adjacent errors due to failures in any t+d basic storage modules, and, because of the translator design, detecting with high probability b-adjacent errors in 2t+2d-1 storage modules where 1

Abstract translation: 公开了新的错误校正和检测代码及其自检翻译器。 这些代码中的第一个是使用bt个校验位的2t + d组的tb相邻位组纠错和t + d b相邻的d相邻位组检错码。 具有b位BSM（基本存储模块）存储器组织的代码能够校正由于任何t个基本存储模块中的故障导致的b相邻错误，检测由于任何t + d个基本存储模块中的故障导致的b相邻错误， 并且由于翻译器设计，在2t + 2d-1个存储模块中检测出具有高概率b相邻误差，其中1

公开(公告)号：US3736569A

公开(公告)日：1973-05-29

申请号：US3736569D

申请日：1971-10-13

Applicant: IBM

Inventor： BOURICIUS W ,  JESSEP D ,  CARTER W ,  WADIA A

IPC: G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F9/06

CPC classification number: G06F9/3802 ,  G06F1/3215 ,  G06F1/3275 ,  G06F9/30083 ,  G06F9/3814 ,  Y02D10/13 ,  Y02D10/14

Abstract: The disclosed system causes power to be removed from the memory for a chosen time duration after each time that the memory is used. The time duration can be chosen as desired and is specified by a ''''WAIT N'''' instruction. When this instruction appears, the power to the memory is removed therefrom and accesses to the memory are prevented. The time duration is entered into a register and the contents of this register are compared with the contents of a counter which has a clock pulse train applied thereto until equality is attained whereby an equality signal issues. The latter signal is applied to restore power to the memory and, with appropriate logic, permits accesses to the memory, read or write, for example. When the memory accessing is completed, the N units specified by the ''''WAIT N'''' instruction would be usable at the option of the program to control access to the memory and to remove power therefrom for the duration of N time units. A new ''''WAIT N'''' instruction can change the time duration.

Abstract translation: 所公开的系统在每次使用存储器之后在所选择的持续时间内导致从存储器中去除功率。 可以根据需要选择持续时间，并由“等待N”指令指定。 当这个指令出现时，从存储器的电源被去除，并阻止对存储器的访问。 将持续时间输入到寄存器中，并将该寄存器的内容与应用了时钟脉冲序列的计数器的内容进行比较，直到达到相等性，从而产生相等的信号。 后一个信号被应用于恢复对存储器的电力，并且通过适当的逻辑允许例如访问存储器，读取或写入。 当存储器访问完成时，由“WAIT N”指令指定的N个单元将可用于该程序的选项，以控制对存储器的访问并且在N个时间单位的持续时间内从其中移除电力。 新的“等待N”指令可以改变持续时间。