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11.发明授权公开(公告)号：US08872593B2
公开(公告)日：2014-10-28
申请号：US13734805
申请日：2013-01-04
申请人： Broadcom Corporation
发明人： Mohyee Mikhemar , Hooman Darabi
CPC分类号： H03B21/00 , G01L9/12 , G01R27/2605 , G01R31/016 , H03B5/20 , H03B5/32 , H03K3/0231 , H03K3/354
摘要： A technique for calibration of on-chip resistance (R) and capacitance (C) values using an on-board bypass capacitor may include configuring an on-chip switch to selectively couple an on-chip calibration circuit to an on-chip port. The on-chip calibration circuit may include an RC oscillator having an RC time constant (RCTC). The on-board bypass capacitor may be coupled to the on-chip calibration circuit, by using the on-chip port. The on-chip R and C values may be calibrated using the on-chip calibration circuit and the on-board bypass capacitor.
摘要翻译： 使用板载旁路电容器来校准片上电阻（R）和电容（C）值的技术可以包括配置片内开关以选择性地将片上校准电路耦合到片上端口。 片上校准电路可以包括具有RC时间常数（RCTC）的RC振荡器。 板上旁路电容器可以通过使用片上端口耦合到片上校准电路。 片内R和C值可以使用片上校准电路和板载旁路电容进行校准。
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公开(公告)号：US08816724B2
公开(公告)日：2014-08-26
申请号：US13715529
申请日：2012-12-14
IPC分类号： H03B21/00
CPC分类号： H03B21/00 , H03L7/1974
摘要： Methods and systems are disclosed that provide a radio frequency synthesizer that generates precise frequencies over a large radio frequency range. The radio frequency synthesizer can provide a high resolution of frequency generation and still provide precise frequencies over a range of radio frequencies. The precision and resolution while maintaining a large operating range come from the ability of the frequency synthesizer to generate frequencies as a product of a plurality of moduli. For example, the frequency can be generated from a reference frequency using a first modulus and a second modulus. The plurality of modulo can be implemented using nested digital delta-sigma modulators in a fractional-N frequency synthesizer.
摘要翻译： 公开了提供在大的射频范围内产生精确频率的射频合成器的方法和系统。 无线电频率合成器可以提供高分辨率的频率产生，并且还能在无线电频率范围内提供精确的频率。 维持较大工作范围的精度和分辨率来自于频率合成器产生频率作为多个模数乘积的能力。 例如，可以使用第一模数和第二模数从参考频率产生频率。 可以使用分数N频率合成器中的嵌套数字Δ-Σ调制器来实现多个模数。
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公开(公告)号：US20140191782A1
公开(公告)日：2014-07-10
申请号：US13734805
申请日：2013-01-04
申请人： BROADCOM CORPORATION
发明人： Mohyee MIKHEMAR , Hooman DARABI
IPC分类号： H03B21/00
CPC分类号： H03B21/00 , G01L9/12 , G01R27/2605 , G01R31/016 , H03B5/20 , H03B5/32 , H03K3/0231 , H03K3/354
摘要： A technique for calibration of on-chip resistance (R) and capacitance (C) values using an on-board bypass capacitor may include configuring an on-chip switch to selectively couple an on-chip calibration circuit to an on-chip port. The on-chip calibration circuit may include an RC oscillator having an RC time constant (RCTC). The on-board bypass capacitor may be coupled to the on-chip calibration circuit, by using the on-chip port. The on-chip R and C values may be calibrated using the on-chip calibration circuit and the on-board bypass capacitor.
摘要翻译： 使用板载旁路电容器来校准片上电阻（R）和电容（C）值的技术可以包括配置片内开关以选择性地将片上校准电路耦合到片上端口。 片上校准电路可以包括具有RC时间常数（RCTC）的RC振荡器。 板上旁路电容器可以通过使用片上端口耦合到片上校准电路。 片内R和C值可以使用片上校准电路和板载旁路电容进行校准。
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14.发明申请Non-Linear-Error Correction in Fractional-N Digital PLL Frequency Synthesizer 有权分数N数字PLL频率合成器中的非线性误差校正公开(公告)号：US20140097875A1
公开(公告)日：2014-04-10
申请号：US13645760
申请日：2012-10-05
IPC分类号： H03B21/00
CPC分类号： H03L7/1976 , H03L7/085
摘要： The present disclosure relates to a frequency synthesizer. The frequency synthesizer includes a phase comparator having first and second input nodes. The first input node receives a reference signal having a reference frequency. A channel control block has an input that receives a channel word and an output coupled to the second input node of the phase comparator. A local oscillator (LO) output node provides an LO signal having an LO frequency based on the reference frequency and the channel word. A feedback back couples the LO output node to the second input node of the phase comparator through the channel control block. A non-linear error correction element is operably coupled on a coupling path extending between the phase comparator and the DCO.
摘要翻译： 本公开涉及频率合成器。 频率合成器包括具有第一和第二输入节点的相位比较器。 第一输入节点接收具有参考频率的参考信号。 信道控制块具有接收信道字的输入和耦合到相位比较器的第二输入节点的输出。 本地振荡器（LO）输出节点基于参考频率和通道字提供具有LO频率的LO信号。 反馈反馈通过信道控制块将LO输出节点耦合到相位比较器的第二输入节点。 非线性误差校正元件可操作地耦合在相位比较器和DCO之间延伸的耦合路径上。
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公开(公告)号：US08648625B2
公开(公告)日：2014-02-11
申请号：US12807982
申请日：2010-09-16
申请人： Kazuo Akaike , Nobuo Tsukamoto , Tsukasa Kobata
发明人： Kazuo Akaike , Nobuo Tsukamoto , Tsukasa Kobata
摘要： There is provided a frequency synthesizer capable of improving phase noise. A sinusoidal signal with a frequency set by a frequency setting part is output as a digital signal from a set signal output part, and the digital signal is D/A-converted. A difference between a sinusoidal signal with a frequency corresponding to an output frequency of a voltage controlled oscillating part and a sinusoidal signal output from a D/A converting part is amplified by a differential amplifier, and an amplified signal is input via an A/D converting part to a means for extracting a phase difference between the aforesaid sinusoidal signals. A voltage corresponding to a signal being the result of integration of the phase difference is input as a control voltage to the voltage controlled oscillating part. Then, a gain of the differential amplifier is set larger than a maximum value of phase noise degradation of the A/D converting part, whereby the phase noise degradation of the A/D converting part is cancelled.
摘要翻译： 提供了能够改善相位噪声的频率合成器。 由频率设定部设定的频率的正弦信号作为来自设定信号输出部的数字信号输出，数字信号进行D / A转换。 具有对应于压控振荡部分的输出频率的频率的正弦信号与从D / A转换部分输出的正弦信号之间的差异由差分放大器放大，放大的信号通过A / D 将部分转换成用于提取上述正弦信号之间的相位差的装置。 将作为相位差积分的结果的信号对应的电压作为控制电压输入到受电压控制的振荡部。 然后，将差分放大器的增益设定为大于A / D转换部分的相位噪声劣化的最大值，从而消除A / D转换部分的相位噪声劣化。
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公开(公告)号：US20130321031A1
公开(公告)日：2013-12-05
申请号：US13482875
申请日：2012-05-29
IPC分类号： H03B21/00
CPC分类号： G06G7/26
摘要： The CMOS programmable non-linear function synthesizer utilizes CMOS current-mode electronics to provide synthesis of arbitrary analog functions. The circuit approximates a seventh-order Taylor series expansion to synthesize an arbitrary nonlinear function. Each term of the Taylor series expansion is realized using a current-mode basic building block, and the output weighted currents of these basic building blocks are algebraically added in addition to a DC current, if needed. The CMOS current mode electronic circuit can be easily integrated, extended to include higher order terms of the Taylor series, and programmed to generate arbitrary nonlinear functions.
摘要翻译： CMOS可编程非线性功能合成器利用CMOS电流模式电子学提供任意模拟功能的综合。 该电路接近七阶泰勒级数展开以合成任意非线性函数。 泰勒级数扩展的每个项目都是使用电流模式的基本构建块实现的，如果需要，除了直流电流之外，这些基本构建块的输出加权电流也被代数地添加。 CMOS电流模式电子电路可以容易地集成，扩展到包括泰勒级数的高阶项，并被编程以产生任意的非线性函数。
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公开(公告)号：US08575972B2
公开(公告)日：2013-11-05
申请号：US12409228
申请日：2009-03-23
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , Y02D10/126
摘要： A first plurality of clock signals including a first clock signal and a second clock signal is received, the first and second clock signal out of phase with each other. A second plurality of clock signals comprising a third clock signal and a fourth clock signal is received, the third and fourth clock signals out of phase with each other. A plurality of enable signals are received. A fifth clock signal is determined based on the first plurality of clock signals and the plurality of enable signals. A sixth clock signal is determined based on the second plurality of clock signals and the plurality of enable signals. A seventh clock signal is determined based on the fifth clock signal and the sixth clock signal.
摘要翻译： 接收包括第一时钟信号和第二时钟信号的第一多个时钟信号，第一和第二时钟信号彼此异相。 接收包括第三时钟信号和第四时钟信号的第二多个时钟信号，第三和第四时钟信号彼此不同相。 接收多个使能信号。 基于第一多个时钟信号和多个使能信号来确定第五时钟信号。 基于第二多个时钟信号和多个使能信号来确定第六时钟信号。 基于第五时钟信号和第六时钟信号确定第七时钟信号。
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公开(公告)号：US20130278295A1
公开(公告)日：2013-10-24
申请号：US13770337
申请日：2013-02-19
发明人： Sung Yeol KIM , Hyun Woo CHOI , Nicholas TZOU , Xian WANG , Thomas MOON , Abhijit CHATTERJEE , Ho Sun YOO
CPC分类号： H03M1/1245 , H03B21/00 , H03M1/121
摘要： An apparatus for measuring a high speed signal may comprise a plurality of Analog-Digital converters (AD converter) that are arranged in parallel to each other to sample an input signal at different frequencies; a plurality of frequency synthesizers configured to provide each AD converter with a different sampling frequency; a signal processor configured to receive an output of the plurality of AD converters to reconstruct the input signal; and/or a controller configured to receive and process a trigger signal.
摘要翻译： 用于测量高速信号的装置可以包括彼此并联布置以对不同频率的输入信号进行采样的多个模数转换器（AD转换器）; 多个频率合成器，被配置为向每个AD转换器提供不同的采样频率; 信号处理器，被配置为接收所述多个AD转换器的输出以重建所述输入信号; 和/或被配置为接收和处理触发信号的控制器。
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公开(公告)号：US20130200925A1
公开(公告)日：2013-08-08
申请号：US13829820
申请日：2013-03-14
申请人： Jose Pedro MOREIRA
发明人： Jose Pedro MOREIRA
IPC分类号： H03B21/00
CPC分类号： H03B21/00 , H03C5/00 , H03M1/66 , H04B1/0475 , H04B1/0483
摘要： Implementations of a high gain range transmitter with variable-size mixers are described.
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公开(公告)号：US20130169315A1
公开(公告)日：2013-07-04
申请号：US13775098
申请日：2013-02-22
发明人： Koichi Wago , Sundeep Chauhan , David M. Tung
CPC分类号： H03L7/06 , H01J37/3174 , H03B21/00 , H03L7/08
摘要： A method for encoder frequency-shift compensation includes determining frequency values of an input encoder signal, determining repeatable frequency-shifts of the frequency values and generating a frequency-shift compensated clock using the repeatable frequency-shifts. A frequency-shift compensated clock includes a synthesizer configured to generate a frequency-shift compensated clock signal using repeatable frequency shifts and encoder clock signals.
摘要翻译： 一种用于编码器频移补偿的方法包括：确定输入编码器信号的频率值，确定频率值的可重复频移，并使用可重复的频移产生频移补偿时钟。 频移补偿时钟包括合成器，其被配置为使用可重复的频移和编码器时钟信号来产生频移补偿的时钟信号。
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