公开(公告)号：US3853974A

公开(公告)日：1974-12-10

申请号：US33429473

申请日：1973-02-21

申请人： SIEMENS AG

发明人： REUSCHEL K ,  DIETZE W

IPC分类号： C01B33/02 ,  C23C16/01 ,  C23C16/24 ,  B01J17/28 ,  B29C13/04

CPC分类号： C23C16/24 ,  C01B33/02 ,  C23C16/01 ,  Y10S148/007 ,  Y10S148/025 ,  Y10S148/027 ,  Y10S148/049 ,  Y10S148/073 ,  Y10S148/122

摘要： An at least unilaterally open hollow body of silicon or other semiconductor material is produced by thermally reducing a gaseous compound of the same material and precipitating the segregated material upon a heated carrier of different material, preferably graphite or other industrial carbon, and thereafter removing the resulting hollow semiconductor body from the carrier. The gaseous compound is supplied to the heated carrier in mixture with a reduction gas, preferably hydrogen, in a molar ratio that substantially corresponds to the reaction equilibrium at the carrier temperature obtaining at the beginning of the reduction and precipitation process. After the precipitated hollow body has reached a layer thickness of a few microns, the molar ratio is changed so as to increase the rate of precipitation. The method can be modified by changing the throughput of the gaseous mixtures from a lower to a higher value after a layer thickness of a few microns has been reached and then continuing the precipitation at a higher rate until the desired full layer thickness is obtained.

摘要翻译： 通过热还原相同材料的气态化合物并将分离的材料沉淀在不同材料，优选石墨或其它工业碳的加热载体上，然后除去所得到的至少单向开放的硅或其它半导体材料的中空体 中空半导体体从载体。 将气态化合物与还原气体（优选氢气）混合加入到加热的载体中，其摩尔比基本上对应于在还原和沉淀过程开始时获得的载体温度下的反应平衡。 在沉淀的中空体已经达到几微米的层厚度之后，改变摩尔比以增加沉淀速率。 可以通过在达到几微米的层厚度之后将气态混合物的生产量从较低值改变为更高的值，然后以更高的速率继续沉淀直到获得所需的全层厚度来修改该方法。

公开(公告)号：US3761757A

公开(公告)日：1973-09-25

申请号：US3761757D

申请日：1971-12-08

申请人： SIEMENS AG

发明人： MUHLBAUER A ,  NAGORSEN H

IPC分类号： H01K1/28 ,  H01K1/32 ,  H01J5/16 ,  H01J61/38

CPC分类号： H01K1/28 ,  H01K1/32 ,  Y10S148/073 ,  Y10S148/122

摘要： In an infrared lamp instead of a glass or quartz bulb, a tube sealed at one end and consisting of pyrolytically precipitated, polycrystalline silicon is used. It is gas-tight even at a wall thickness of 0.5 mm and mechanically stable even at elevated temperatures, up to 1,300* C. Silicon possesses a distinct filter effect and is permeable only to beams with a wave length greater than 1.1 Mu .

摘要翻译： 在红外灯代替玻璃或石英灯泡中，使用在一端密封并由热解沉淀的多晶硅组成的管。 即使在0.5mm的壁厚下也是气密的，甚至在高达1300℃的高温下也是机械稳定的。硅具有不同的过滤效果，并且仅对波长大于1.1μm的光束是可透过的。

公开(公告)号：US3748169A

公开(公告)日：1973-07-24

申请号：US3748169D

申请日：1972-03-15

申请人： SIEMENS AG

发明人： KELLER W

IPC分类号： C23C16/22 ,  C23C11/00 ,  C23C11/06

CPC分类号： C23C16/22 ,  Y10S148/073 ,  Y10S148/122 ,  Y10S148/135

摘要： A METHOD FOR THE PRODUCTION OF HOLLOW MEMBERS OF SEMICONDUCTOR MATERIAL OF ANY LENGTH BY THERMAL DECOMPOSITION OF A GASEOUS COMPOUND CONTAINING SEMICONDUCTOR MATERIAL IS DESCRIBED. PREFERABLY, A HOLLOW MEMBER OF GRAPHITE OR SILICON IS EMPOLYED AS A CARRIER ON THE FRONTAL SURFACE OF WHICH SEMICONDUCTOR MATERIAL IS DEPOSITED IN RESPONSE TO THE CREATION OF A TEMPERATURE GRADIENT ALONG THE CARRIER MEMBER. THE HALLOW MEMBER IS MOVED OUT OF THE DEPOSITING ZONE AT THE RATE OF DEPOSITION OF THE SEMICONDUCTOR MATERIAL.

公开(公告)号：US06645850B2

公开(公告)日：2003-11-11

申请号：US10230753

申请日：2002-08-29

申请人： Rainer Leuschner ,  Egon Mergenthaler

发明人： Rainer Leuschner ,  Egon Mergenthaler

IPC分类号： H01L214763

CPC分类号： H01L21/7682 ,  H01L21/31111 ,  Y10S148/073

摘要： A method creates structured cavities with submicrometer dimensions in a cavity layer of a semiconductor device. A processing material that incorporates a swelling agent is deposited on ridges of a working layer that is constructed of ridges and trenches. The processing material expands over the trenches during swelling; and covered cavities thus emerge from the trenches.

摘要翻译： 一种方法在半导体器件的空腔层中产生具有亚微米尺寸的结构化空腔。 掺有溶胀剂的处理材料沉积在由脊和沟构成的工作层的脊上。 处理材料在膨胀期间在沟槽上膨胀; 并且覆盖的空腔因此从沟槽中出现。

公开(公告)号：US20030049914A1

公开(公告)日：2003-03-13

申请号：US10230753

申请日：2002-08-29

发明人： Rainer Leuschner ,  Egon Mergenthaler

IPC分类号： H01L021/76 ,  H01L021/4763

CPC分类号： H01L21/7682 ,  H01L21/31111 ,  Y10S148/073

摘要： A method creates structured cavities with submicrometer dimensions in a cavity layer of a semiconductor device. A processing material that incorporates a swelling agent is deposited on ridges of a working layer that is constructed of ridges and trenches. The processing material expands over the trenches during swelling; and covered cavities thus emerge from the trenches.

公开(公告)号：US5828121A

公开(公告)日：1998-10-27

申请号：US668518

申请日：1996-06-27

申请人： Water Lur ,  Jiunn Yuan Wu

发明人： Water Lur ,  Jiunn Yuan Wu

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485 ,  H01L23/535 ,  H01L29/41

CPC分类号： H01L23/5226 ,  H01L21/7682 ,  H01L23/5221 ,  H01L23/5222 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53242 ,  H01L23/53247 ,  H01L2924/0002 ,  Y10S148/073

摘要： This invention deals with the formation of the multi-level electrode metal structure and the interconnecting inter-level metal studs used in the fabrication of VLSI circuits. After the metal layers have been formed the inter-level dielectric material used in forming the structure is etched away leaving an air dielectric between the levels. The electrode metal and the inter-level metal studs are coated with a thin envelope oxide and the entire structure is covered with a passivation layer using material with a poor step coverage. The structure of this invention provides reduced parasitic capacitance, better step coverage in interconnecting layers, and improved circuit performance.

摘要翻译： 本发明涉及在制造VLSI电路中使用的多层电极金属结构和互连层间金属柱的形成。 在形成金属层之后，用于形成结构的层间介电材料被蚀刻掉，留下两层之间的空气电介质。 电极金属和层间金属螺柱涂有薄膜氧化物，整个结构用钝化层覆盖，使用的步骤覆盖率差。 本发明的结构提供减小的寄生电容，互连层中的更好的步骤覆盖和改进的电路性能。

公开(公告)号：US5640041A

公开(公告)日：1997-06-17

申请号：US609260

申请日：1996-02-29

申请人： Water Lur ,  Edward Houn

发明人： Water Lur ,  Edward Houn

IPC分类号： H01L21/308 ,  H01L21/311 ,  H01L21/336 ,  H01L21/762 ,  H01L21/763 ,  H01L29/00

CPC分类号： H01L29/6659 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/763 ,  H01L29/6656 ,  Y10S148/073 ,  Y10S257/90 ,  Y10S438/938

摘要： A new method of trench isolation incorporating thermal stress releasing voids is described. Two sets of narrow trenches are etched into the silicon substrate not covered by a photoresist mask wherein the second set of trenches alternate with the first set of trenches. The first set of trenches is filled with an insulating layer. A second insulating layer is deposited over the surface of the substrate and within the second set of trenches wherein said insulating layer has step coverage such that voids are formed and are completely enclosed within the second set of trenches completing the thermal stress releasing device isolation of the integrated circuit. The method of forming thermal stress released polysilicon gate spacers in an integrated circuit is described. Polysilicon gate electrodes are formed on the surface of the semiconductor substrate. Sucessive sidewalls are formed on the gate electrodes of thin silicon dioxide, silicon nitride, and silicon dioxide. The silicon nitride spacers are removed leaving trenches between the thin silicon dioxide sidewalls and the silicon dioxide spacers. A thin insulating material is deposited over the surface of the gate electrodes and the sidewalls with a step coverage such that the trenches between the thin oxidation and the silicon dioxide spacers are not filled by the thin insulating layer but are covered by the thin insulating layer leaving voids which complete the thermal stress released polysilicon gate spacer formation in the fabrication of an integrated circuit.

公开(公告)号：US5516720A

公开(公告)日：1996-05-14

申请号：US195090

申请日：1994-02-14

申请人： Water Lur ,  Edward Houn

发明人： Water Lur ,  Edward Houn

IPC分类号： H01L21/308 ,  H01L21/311 ,  H01L21/336 ,  H01L21/762 ,  H01L21/763 ,  H01L21/31

CPC分类号： H01L29/6659 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/763 ,  H01L29/6656 ,  Y10S148/073 ,  Y10S257/90 ,  Y10S438/938

摘要： A new method of trench isolation incorporating thermal stress releasing voids is described. Two sets of narrow trenches are etched into the silicon substrate not covered by a photoresist mask wherein the second set of trenches alternate with the first set of trenches. The first set of trenches is filled with an insulating layer. A second insulating layer is deposited over the surface of the substrate and within the second set of trenches wherein said insulating layer has step coverage such that voids are formed and are completely enclosed within the second set of trenches completing the thermal stress releasing device isolation of the integrated circuit. The method of forming thermal stress released polysilicon gate spacers in an integrated circuit is described. Polysilicon gate electrodes are formed on the surface of the semiconductor substrate. Successive sidewalls are formed on the gate electrodes of thin silicon dioxide, silicon nitride, and silicon dioxide. The silicon nitride spacers are removed leaving trenches between the thin silicon dioxide sidewalls and the silicon dioxide spacers. A thin insulating material is deposited over the surface of the gate electrodes and the sidewalls with a step coverage such that the trenches between the thin oxidation and the silicon dioxide spacers are not filled by the thin insulating layer but are covered by the thin insulating layer leaving voids which complete the thermal stress released polysilicon gate spacer formation in the fabrication of an integrated circuit.

摘要翻译： 描述了一种结合热应力释放空隙的新型沟槽隔离方法。 将两组窄沟槽蚀刻到未被光致抗蚀剂掩模覆盖的硅衬底中，其中第二组沟槽与第一组沟槽交替。 第一组沟槽填充有绝缘层。 第二绝缘层沉积在衬底的表面上并在第二组沟槽内，其中所述绝缘层具有阶梯覆盖，使得形成空隙并完全封闭在第二组沟槽内，从而完成热应力释放装置的隔离 集成电路。 描述了在集成电路中形成热应力释放多晶硅栅极间隔物的方法。 多晶硅栅电极形成在半导体衬底的表面上。 在薄二氧化硅，氮化硅和二氧化硅的栅电极上形成连续的侧壁。 去除氮化硅间隔物，留下薄二氧化硅侧壁和二氧化硅间隔物之间​​的沟槽。 薄的绝缘材料沉积在栅电极和侧壁的表面上，具有台阶覆盖，使得薄氧化物和二氧化硅间隔物之间​​的沟槽不被薄绝缘层填充，但被薄绝缘层覆盖，离开 完成热应力的空隙在集成电路的制造中释放多晶硅栅极间隔物的形成。

公开(公告)号：US5328868A

公开(公告)日：1994-07-12

申请号：US989742

申请日：1992-12-10

申请人： Richard A. Conti ,  Kenneth DeVries ,  James F. White

发明人： Richard A. Conti ,  Kenneth DeVries ,  James F. White

IPC分类号： H01L21/768 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L21/76877 ,  Y10S148/05 ,  Y10S148/073

摘要： A metal connection for an integrated circuit device is effectively "cast" in place at any level of an integrated circuit. The "mold" for the connection is formed by depositing and patterning a sacrificial material, such as aluminum oxide or other metal oxides, and covering the sacrificial material with a protective material such as silicon dioxide or other insulators. After forming bore holes to the deposit of sacrificial material through the protective layer, the sacrificial material is removed by isotropic etching to form a cavity beneath and at least partially overlaid by the protective layer. Alternatively, a defect may be produced below the protective layer and filled with metal either with or without enlargement by further removal of material. This cavity is then filled with metal by deposition of the metal by, for instance, evaporation, sputtering and chemical vapor deposition or combinations thereof. Connections formed by this technique can be produced at any level of the integrated circuit and do not interfere with surface wiring. A plurality of such connections may be simultaneously formed at the same or different levels of the integrated circuit and the method may be repeated to form multi-level wiring patterns.

摘要翻译： 用于集成电路器件的金属连接在集成电路的任何级别上有效地“铸造”到位。 用于连接的“模具”通过沉积和图案化牺牲材料（例如氧化铝或其它金属氧化物）并用诸如二氧化硅或其它绝缘体的保护材料覆盖牺牲材料而形成。 在通过保护层沉积牺牲材料的孔之后，通过各向同性蚀刻去除牺牲材料，以在保护层下方并且至少部分地覆盖保护层。 或者，可以在保护层下面产生缺陷，并通过进一步去除材料来填充有或没有放大的金属。 然后通过例如蒸发，溅射和化学气相沉积或其组合通过沉积金属来填充该空腔。 通过该技术形成的连接可以在集成电路的任何级别产生，并且不会干扰表面布线。 可以在集成电路的相同或不同级别同时形成多个这样的连接，并且可以重复该方法以形成多层布线图案。

公开(公告)号：US5156978A

公开(公告)日：1992-10-20

申请号：US731118

申请日：1991-07-15

申请人： Balakrishnan R. Bathey ,  Mary C. Cretalla ,  Aaron S. Taylor

发明人： Balakrishnan R. Bathey ,  Mary C. Cretalla ,  Aaron S. Taylor

IPC分类号： C30B15/00 ,  C30B15/04 ,  C30B15/34 ,  H01L31/0224 ,  H01L31/0288 ,  H01L31/18

CPC分类号： H01L31/182 ,  C30B15/00 ,  C30B15/04 ,  C30B15/34 ,  C30B29/60 ,  H01L31/022425 ,  H01L31/0288 ,  Y02E10/546 ,  Y02P70/521 ,  Y10S148/073 ,  Y10S438/913 ,  Y10T117/104

摘要： A method and apparatus for producing crystalline substrate for use in fabricating solid state electronic devices. A hollow crystalline body is grown from a melt containing a dopant and a P-N junction is formed in said crystalline body as it is being grown. Then the hollow body is severed to provide individual solar cell substrates.

摘要翻译： 一种用于制造用于制造固态电子器件的结晶衬底的方法和装置。 从包含掺杂剂的熔体中生长中空的结晶体，并且在所述晶体生长中形成P-N结。 然后中空体被切断以提供单独的太阳能电池基板。