公开(公告)号：US20100020599A1

公开(公告)日：2010-01-28

申请号：US12178174

申请日：2008-07-23

Applicant: LIH WEI LIN ,  WEI SHENG HSU ,  YAN RU YANG ,  YEN WEN CHEN

Inventor： LIH WEI LIN ,  WEI SHENG HSU ,  YAN RU YANG ,  YEN WEN CHEN

IPC: G11C16/04

CPC classification number: H01L29/7923 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/7887

Abstract: A multi-level flash memory comprises a semiconductor substrate, a gate structure having a lower block positioned in the semiconductor substrate and an upper block positioned on the semiconductor substrate, and a plurality of storage structures separated by the gate structure. The upper block connects to the lower block of the gate structure, and each of the storage structures includes a charge-trapping site and an insulation structure surrounding the charge-trapping site.

Abstract translation: 多级闪速存储器包括半导体衬底，具有位于半导体衬底中的下部块的栅极结构和位于半导体衬底上的上部块，以及由栅极结构分离的多个存储结构。 上部块连接到栅极结构的下部块，并且每个存储结构包括电荷捕获位置和围绕电荷捕获位点的绝缘结构。

公开(公告)号：US20100012996A1

公开(公告)日：2010-01-21

申请号：US12174067

申请日：2008-07-16

Applicant: TSUNG DE LIN

Inventor： TSUNG DE LIN

IPC: H01L29/94

CPC classification number: H01L27/10855 ,  H01L21/76889

Abstract: A dynamic random access memory structure comprises a substrate having a first diffusion region and a second diffusion region, a dielectric structure overlaying the substrate, a capacitor contact plug disposed in the dielectric structure and connected to the first diffusion region, a bit-line contact plug disposed in the dielectric structure and connected to the second diffusion region, a metal silicide disposed on the capacitor contact plug, and a capacitive structure disposed on the dielectric structure and connected to the metal silicide.

Abstract translation: 动态随机存取存储器结构包括具有第一扩散区和第二扩散区的衬底，覆盖衬底的电介质结构，设置在电介质结构中并连接到第一扩散区的电容器接触插塞，位线接触插塞 设置在电介质结构中并连接到第二扩散区，设置在电容器接触插塞上的金属硅化物，以及设置在电介质结构上并连接到金属硅化物的电容结构。

公开(公告)号：US20090291548A1

公开(公告)日：2009-11-26

申请号：US12124101

申请日：2008-05-20

Applicant: YUAN MING CHANG ,  CHENG DA WU ,  DA YU CHUANG ,  YEN TA CHEN

Inventor： YUAN MING CHANG ,  CHENG DA WU ,  DA YU CHUANG ,  YEN TA CHEN

IPC: H01L21/28

CPC classification number: H01L21/28017 ,  H01L21/32155 ,  H01L21/324

Abstract: A method for preparing a P-type polysilicon gate structure comprises the steps of forming a gate oxide layer on a substrate, forming an N-type polysilicon layer on the gate oxide layer, performing a first implanting process to convert the N-type polysilicon layer into a P-type polysilicon layer, performing a second implanting process to implant P-type dopants into a portion of the P-type polysilicon layer near the interface between the gate oxide layer and the P-type polysilicon layer, and performing a thermal treating process at a predetermined temperature for a predetermined period to complete the P-type polysilicon gate structure.

Abstract translation: 一种制备P型多晶硅栅结构的方法，包括以下步骤：在衬底上形成栅极氧化层，在栅极氧化层上形成N型多晶硅层，进行第一注入工艺以将N型多晶硅层 进入P型多晶硅层，进行第二注入工序，将P型掺杂剂注入到栅极氧化层和P型多晶硅层之间的界面附近的P型多晶硅层的一部分中，进行热处理 在预定温度下处理预定时间以完成P型多晶硅栅极结构。

公开(公告)号：US07582524B2

公开(公告)日：2009-09-01

申请号：US11529502

申请日：2006-09-29

Applicant: Jung Wu Chien ,  Chia Shun Hsiao

Inventor： Jung Wu Chien ,  Chia Shun Hsiao

IPC: H01L21/8242

CPC classification number: H01L27/105 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for preparing a memory structure comprises the steps of forming a plurality of line-shaped blocks on a dielectric structure of a substrate, and forming a first etching mask exposing a sidewall of the line-shaped blocks. A portion of the line-shaped blocks is removed incorporating the first etching mask to reduce the width of the line-shaped blocks to form a second etching mask including a plurality of first blocks and second blocks arranged in an interlaced manner. Subsequently, a portion of the dielectric structure not covered by the second etching mask is removed to form a plurality of openings in the dielectric structure, and a conductive plug is formed in each of the openings. The plurality of openings includes first openings positioned between the first blocks and second openings positioned between the second blocks, and the first opening and the second opening extend to opposite sides of an active area.

Abstract translation: 一种用于制备存储器结构的方法包括以下步骤：在衬底的电介质结构上形成多个线状块，并形成露出线状块的侧壁的第一蚀刻掩模。 除去包含第一蚀刻掩模的线状块的一部分以减小线状块的宽度，以形成包括以隔行方式布置的多个第一块和第二块的第二蚀刻掩模。 随后，去除未被第二蚀刻掩模覆盖的介电结构的一部分，以在电介质结构中形成多个开口，并且在每个开口中形成导电插塞。 多个开口包括位于第一块之间的第一开口和位于第二块之间的第二开口，并且第一开口和第二开口延伸到有源区域的相对侧。

公开(公告)号：US07569845B2

公开(公告)日：2009-08-04

申请号：US11552492

申请日：2006-10-24

Applicant: Yi-Chan Chen ,  Wen-Han Wang

Inventor： Yi-Chan Chen ,  Wen-Han Wang

IPC: H01L47/00

CPC classification number: H01L45/124 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1691

Abstract: A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are electrically connected via the first phase-change material. Since the phase-change material can have a diameter less than the resolution limit of the photolithography process, an operating current for a state conversion of the phase-change material pattern may be reduced so as to decrease a power dissipation of the phase-change memory device.

Abstract translation: 相变存储器包括形成在基板上的底部电极。 在底部电极上形成第一隔离层。 顶部电极形成在隔离层上。 第一相变材料形成在第一隔离层中，其中顶部电极和底部电极经由第一相变材料电连接。 由于相变材料的直径可以小于光刻工艺的分辨率极限，所以可以减小相变材料图案的状态转换的工作电流，从而降低相变存储器的功耗 设备。

公开(公告)号：US07557407B2

公开(公告)日：2009-07-07

申请号：US11435848

申请日：2006-05-18

Applicant: Ting Sing Wang

Inventor： Ting Sing Wang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/42368 ,  H01L21/28141 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/7834

Abstract: A recessed gate structure comprises a semiconductor substrate, a recess positioned in the semiconductor substrate, a gate oxide layer positioned in the recess and a conductive layer positioned on the gate oxide layer, wherein the semiconductor substrate has a multi-step structure in the recess. The thickness of the gate oxide layer on one step surface can be different from that on another step surface of the multi-step structure. In addition, the recessed gate structure further comprises a plurality of doped regions positioned in the semiconductor substrate under the multi-step structure, and these doped regions may use different dosages and different types of dopants. There is a carrier channel in the semiconductor substrate under the recessed gate structure and the overall channel length of the carrier channel is substantially the summation of the lateral width and twice of the vertical depth of the recessed gate structure.

Abstract translation: 凹陷栅极结构包括半导体衬底，位于半导体衬底中的凹部，位于凹槽中的栅极氧化物层和位于栅极氧化物层上的导电层，其中半导体衬底在凹部中具有多级结构。 一步表面上的栅极氧化层的厚度可以与多步结构的另一台阶表面上的厚度不同。 此外，凹陷栅极结构还包括在多步结构下定位在半导体衬底中的多个掺杂区域，并且这些掺杂区域可以使用不同的剂量和不同类型的掺杂剂。 在凹陷栅极结构下方的半导体衬底中存在载流子通道，并且载流子通道的整体沟道长度基本上是凹入栅极结构的横向宽度和垂直深度的两倍的总和。

公开(公告)号：US20090141548A1

公开(公告)日：2009-06-04

申请号：US12273414

申请日：2008-11-18

Applicant: Wen-Pin LIN ,  Shyh-Shyuan SHEU ,  Lieh-Chiu LIN ,  Pei-Chia CHIANG

Inventor： Wen-Pin LIN ,  Shyh-Shyuan SHEU ,  Lieh-Chiu LIN ,  Pei-Chia CHIANG

IPC: G11C5/14 ,  G11C11/00

CPC classification number: G11C8/08 ,  G11C11/4085 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2207/2227 ,  G11C2213/79

Abstract: Memories with low power consumption and methods for suppressing current leakage of a memory. The memory cell of the memory has a storage element and a transistor coupled in series. The invention sets a voltage across the transistor approaching to zero when the memory is not been accessed.

Abstract translation: 具有低功耗的存储器和用于抑制存储器的电流泄漏的方法。 存储器的存储单元具有串联耦合的存储元件和晶体管。 当存储器未被访问时，本发明将跨越晶体管的电压设置为零。

公开(公告)号：US07524732B2

公开(公告)日：2009-04-28

申请号：US11465881

申请日：2006-08-21

Applicant: Chung-We Pan ,  Shi-Cheng Lin ,  Ching-Hung Fu ,  Chih-Ping Chung

Inventor： Chung-We Pan ,  Shi-Cheng Lin ,  Ching-Hung Fu ,  Chih-Ping Chung

IPC: H01L21/20

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521

Abstract: A semiconductor device with an L-shape spacer and the method for manufacturing the same are provided. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer. The substrate comprises a shallow trench isolation structure and a neighboring active area. The composite spacer is formed on the sidewall of the shallow trench isolation structure, and further comprises a first insulating layer and an L-shape second insulating layer spacer, wherein the first insulating layer is located between the L-shape second insulating layer spacer and the substrate. The tunnel insulating layer is located on the substrate of the active area and connects to the first insulating layer of the composite spacer on its corresponding side.

Abstract translation: 提供具有L形间隔物的半导体器件及其制造方法。 半导体器件包括衬底，复合间隔物和隧道绝缘层。 衬底包括浅沟槽隔离结构和相邻有源区。 复合间隔物形成在浅沟槽隔离结构的侧壁上，还包括第一绝缘层和L形第二绝缘层间隔物，其中第一绝缘层位于L形第二绝缘层间隔物和 基质。 隧道绝缘层位于有源区的衬底上，并与其相应侧上的复合衬垫的第一绝缘层相连。

公开(公告)号：US20090065758A1

公开(公告)日：2009-03-12

申请号：US12020494

申请日：2008-01-25

Applicant: Te-Sheng Chao

Inventor： Te-Sheng Chao

IPC: H01L45/00 ,  H01L21/02

CPC classification number: H01L45/144 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675 ,  Y10S438/90

Abstract: A phase change memory array is disclosed, comprising a first cell having a patterned phase change layer, and a second cell having a patterned phase change layer, wherein the patterned phase change layer of the first cell and the patterned phase change layer of the second cell are disposed at different layers.

Abstract translation: 公开了一种相变存储器阵列，其包括具有图案化相变层的第一单元和具有图案化相变层的第二单元，其中第一单元的图案化相变层和第二单元的图案化相变层 被布置在不同的层。

公开(公告)号：US20090061635A1

公开(公告)日：2009-03-05

申请号：US12108285

申请日：2008-04-23

Applicant: Hsiao-Che WU ,  Ming-Yen Li ,  Wen-Li Tsai

Inventor： Hsiao-Che WU ,  Ming-Yen Li ,  Wen-Li Tsai

IPC: H01L21/311

CPC classification number: H01L21/0337

Abstract: A method for forming micro-patterns is disclosed. The method forms a sacrificial layer and a mask layer. A plurality of first taper trenches is formed in the sacrificial layer. A photoresist layer is filled in the plurality of first taper trenches. The photoresist layer is used as a mask and a plurality of second taper trenches is formed in the sacrificial layer. Then, the photoresist layer is stripped to be capable of patterning a layer by the first taper trenches and the second taper trenches in the sacrificial layer. Therefore, a patterned sacrificial layer duplicating the line density by double etching is formed.

Abstract translation: 公开了一种形成微图案的方法。 该方法形成牺牲层和掩模层。 在牺牲层中形成多个第一锥形沟槽。 在多个第一锥形沟槽中填充光致抗蚀剂层。 光致抗蚀剂层用作掩模，并且在牺牲层中形成多个第二锥形沟槽。 然后，剥离光致抗蚀剂层以能够通过第一锥形沟槽和牺牲层中的第二锥形沟槽图案化层。 因此，形成通过双蚀刻复制线密度的图案化牺牲层。