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11.发明授权公开(公告)号：US11909391B1
公开(公告)日：2024-02-20
申请号：US17648112
申请日：2022-01-14
发明人： Amrita Mathuriya , Nabil Imam , Ikenna Odinaka , Rafael Rios , Rajeev Kumar Dokania , Sasikanth Manipatruni
IPC分类号： H03K19/00 , G06F30/398 , H03K19/23
CPC分类号： H03K19/0021 , G06F30/398 , H03K19/23
摘要： Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.
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公开(公告)号：US11901891B1
公开(公告)日：2024-02-13
申请号：US17648122
申请日：2022-01-14
发明人： Amrita Mathuriya , Nabil Imam , Ikenna Odinaka , Rafael Rios , Rajeev Kumar Dokania , Sasikanth Manipatruni
CPC分类号： H03K19/0008 , H03K19/0021 , H03K19/23
摘要： Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.
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公开(公告)号：US11899613B1
公开(公告)日：2024-02-13
申请号：US17408251
申请日：2021-08-20
发明人： Amrita Mathuriya , Christopher B. Wilkerson , Rajeev Kumar Dokania , Debo Olaosebikan , Sasikanth Manipatruni
CPC分类号： G06F15/7825 , G06F9/4881 , G06F9/5027 , G06F9/54 , G06F15/7821 , G06F15/7842
摘要： A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.
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公开(公告)号：US20240047426A1
公开(公告)日：2024-02-08
申请号：US18358552
申请日：2023-07-25
IPC分类号： H01L25/065 , H01L23/525 , G06F9/50 , H01L23/00 , G11C7/10 , G11C11/419 , H10B10/00
CPC分类号： H01L25/0657 , H01L23/525 , G06F9/5077 , H01L24/73 , G11C7/1006 , G11C11/419 , H10B10/00 , H01L2224/32145
摘要： Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.
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公开(公告)号：US11894417B2
公开(公告)日：2024-02-06
申请号：US17649899
申请日：2022-02-03
发明人： Niloy Mukherjee , Somilkumar J. Rathi , Jason Y. Wu , Pratyush Pandey , Zeying Ren , FNU Atiquzzaman , Gabriel Antonio Paulius Velarde , Noriyuki Sato , Mauricio Manfrini , Tanay Gosavi , Rajeev Kumar Dokania , Amrita Mathuriya , Ramamoorthy Ramesh , Sasikanth Manipatruni
IPC分类号： H01L21/768 , H01L21/324 , H10B53/30 , H10N70/20 , H10N70/00 , H01L23/522 , H01L49/02
CPC分类号： H01L28/57 , H01L21/324 , H01L21/76832 , H01L28/65 , H01L28/75 , H10B53/30 , H10N70/8836
摘要： A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.
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公开(公告)号：US11862517B1
公开(公告)日：2024-01-02
申请号：US17553486
申请日：2021-12-16
发明人： Noriyuki Sato , Niloy Mukherjee , Mauricio Manfrini , Tanay Gosavi , Rajeev Kumar Dokania , Somilkumar J. Rathi , Amrita Mathuriya , Sasikanth Manipatruni
IPC分类号： H01L21/00 , H01L21/768 , H01L23/538 , G11C11/22 , H10B53/20
CPC分类号： H01L21/76877 , G11C11/221 , H01L21/76802 , H01L23/5384 , H10B53/20
摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.
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公开(公告)号：US11861278B1
公开(公告)日：2024-01-02
申请号：US17515012
申请日：2021-10-29
发明人： Ikenna Odinaka , Sasikanth Manipatruni , Darshak Doshi , Rajeev Kumar Dokania , Amrita Mathuriya
IPC分类号： G06F30/327 , G06F30/398 , G06F30/3953 , G06F18/22
CPC分类号： G06F30/327 , G06F18/22 , G06F30/398 , G06F30/3953
摘要： A computer-aided design (CAD) tool is provided for logic optimization and synthesis. The CAD tool executes a process that involves optimizing power, performance, and area (PPA) of a logic circuit by minimizing a number of CMOS gates, and majority and/or minority gates in the circuit and its depth. The CAD tool implements a methodology of optimizing logic synthesis based on a mix of standard cell libraries (such as AND, OR, NAND, NOR, XOR, Multiplexer, full adder, half adder, etc.) and varying input majority and minority gates (where the number of inputs in the minority and majority gates could vary as odd numbers from 3 and above). The standard cell libraries cells may contain minority and/or majority gates.
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公开(公告)号：US11844203B1
公开(公告)日：2023-12-12
申请号：US17553469
申请日：2021-12-16
发明人： Noriyuki Sato , Niloy Mukherjee , Mauricio Manfrini , Tanay Gosavi , Rajeev Kumar Dokania , Somilkumar J. Rathi , Amrita Mathuriya , Sasikanth Manipatruni
CPC分类号： H10B53/20 , G11C11/221 , H01L28/75
摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.
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19.发明授权公开(公告)号：US11832451B1
公开(公告)日：2023-11-28
申请号：US17396609
申请日：2021-08-06
发明人： Debraj Guhabiswas , Maria Isabel Perez , Jason Y. Wu , James David Clarkson , Gabriel Antonio Paulius Velarde , Niloy Mukherjee , Noriyuki Sato , Amrita Mathuriya , Sasikanth Manipatruni , Ramamoorthy Ramesh
摘要： Non lead-based perovskite ferroelectric devices for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.
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公开(公告)号：US11817140B1
公开(公告)日：2023-11-14
申请号：US17532647
申请日：2021-11-22
IPC分类号： G11C11/22
CPC分类号： G11C11/2273 , G11C11/2255 , G11C11/2257 , G11C11/2275 , G11C11/2297
摘要： A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.
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