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    Semiconductor device and method for the same
    11.
    发明申请
    Semiconductor device and method for the same 审中-公开
    半导体装置及其方法相同

    公开(公告)号：US20090051034A1

    公开(公告)日：2009-02-26

    申请号：US11892103

    申请日：2007-08-20

    Applicant: Chih-Yang Pai ,  Yuan-Hung Liu ,  Michael Kuang ,  Kuo-Ching Huang

    Inventor： Chih-Yang Pai ,  Yuan-Hung Liu ,  Michael Kuang ,  Kuo-Ching Huang

    IPC: H01L23/52 ,  H01L21/44

    CPC classification number: H01L27/10888 ,  H01L21/76844

    Abstract: A method for forming a semiconductor device is provided. The method includes the following steps. A substrate having a first contact is provided. A layered structure is formed on the substrate. A recess is formed into the layered structure to expose at least a portion of the first contact. A glue layer is formed on the layered structure and the at least a portion of the first contact. The glue layer is removed from the at least a portion of the first contact. A second contact is formed contacting the first contact and the glue layer.

    Abstract translation: 提供一种形成半导体器件的方法。 该方法包括以下步骤。 提供具有第一触点的基板。 在基板上形成层状结构。 形成层状结构中的凹部以暴露第一接触件的至少一部分。 在层状结构和第一接触的至少一部分上形成胶层。 胶层从第一接触件的至少一部分去除。 形成接触第一接触和胶层的第二接触。

    High efficiency thin film inductor
    14.
    发明授权
    High efficiency thin film inductor 有权
    高效薄膜电感

    公开(公告)号：US06373369B2

    公开(公告)日：2002-04-16

    申请号：US09839927

    申请日：2001-04-23

    Applicant: Kuo-Ching Huang ,  Jin-Yuan Lee ,  Tse-Liang Ying

    Inventor： Kuo-Ching Huang ,  Jin-Yuan Lee ,  Tse-Liang Ying

    IPC: H01F500

    CPC classification number: H01F5/003

    Abstract: An improved thin film inductor design is described. A spiral geometry is used to which has been added a core of high permeability material located at the center of the spiral. If the high permeability material is a conductor, care must be taken to avoid any contact between the core and the spiral. If a dielectric ferromagnetic material is used, this constraint is removed from the design. Several other embodiments are shown in which, in addition to the high permeability core, provide low reluctance paths for the structure. In one case this takes the form of a frame of ferromagnetic material surrounding the spiral while in a second case it has the form of a hollow square located directly above the spiral.

    Abstract translation: 描述了改进的薄膜电感器设计。 使用螺旋几何形状，其中已经添加了位于螺旋中心的高磁导率材料的核心。 如果高导磁率材料是导体，则必须注意避免芯和螺旋之间的任何接触。 如果使用介电铁磁材料，则从设计中去除该约束。 示出了其中除了高磁导率芯之外还提供用于结构的低磁阻路径的其它实施例。 在一种情况下，这采取围绕螺旋的铁磁材料框架的形式，而在第二种情况下，其具有直接位于螺旋上方的中空正方形的形式。

    Method for fabricating a self aligned contact which eliminates the key hole problem using a two step spacer deposition
    15.
    发明授权
    Method for fabricating a self aligned contact which eliminates the key hole problem using a two step spacer deposition 有权
    用于制造自对准接触的方法，其消除使用两步间隔物沉积的键孔问题

    公开(公告)号：US06214715B1

    公开(公告)日：2001-04-10

    申请号：US09349841

    申请日：1999-07-08

    Applicant: Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

    Inventor： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

    IPC: H01L2144

    CPC classification number: H01L27/10855 ,  H01L21/76897 ,  H01L27/10885 ,  H01L28/91 ,  H01L28/92

    Abstract: This invention provides a method for forming a self aligned contact without key holes using a two step sidewall spacer deposition. The process begins by providing a semiconductor structure having a device layer, a first inter poly oxide layer (IPO-1), and a conductive structure (such as a bit line) thereover, and having a contact area on the device layer adjacent to the conductive structure. The semiconductor structure can further include an optional etch stop layer overlying the first inter poly oxide layer. The conductive structure comprises at least one conductive layer with a hard mask thereover. A first spacer layer is formed over the hard mask and the IPO-1 layer and anisotropically etched to form first sidewall spacers on the sidewalls of the conductive structure up to a level above the bottom of the hard mask and below the level of the top of the hard mask such that the profile of the first sidewall spacers are not concave at any point. A second spacer layer is formed over the first sidewall spacers and anisotropically etched to form second sidewall spacers, having a profile that is not concave at any point. A second inter poly oxide layer is formed over the second sidewall spacers, the hard mask, and the IPO-1 layer, whereby the second inter poly oxide layer is free from key holes. A contact opening is formed in the second inter poly oxide layer and the first inter poly oxide layer over the contact area. A contact plug is formed in the contact openings.

    Abstract translation: 本发明提供一种用于使用两步侧壁间隔物沉积形成无键孔的自对准接触的方法。 该过程开始于提供具有器件层，第一多晶硅氧化物层（IPO-1）和导电结构（例如位线）的半导体结构，并且在与其相邻的器件层上具有接触区域 导电结构。 半导体结构还可以包括覆盖在第一多晶硅氧化物层上的任选的蚀刻停止层。 导电结构包括至少一个具有硬掩模的导电层。 在硬掩模和IPO-1层上形成第一间隔层，并且各向异性蚀刻以在导电结构的侧壁上形成直到硬掩模的底部以上的水平并且低于 硬掩模，使得第一侧壁隔片的轮廓在任何点都不是凹的。 第二间隔层形成在第一侧壁间隔物上并且各向异性蚀刻以形成第二侧壁间隔物，其具有在任何点处不凹的轮廓。 在第二侧壁间隔物，硬掩模和IPO-1层上形成第二多晶硅氧化物层，由此第二多晶氧化物层没有键孔。 在接触区域上的第二多晶氧化物层和第一多晶氧化物层中形成接触开口。 在接触开口中形成接触塞。

    Technology for high performance buried contact and tungsten polycide gate integration
    16.
    发明授权
    Technology for high performance buried contact and tungsten polycide gate integration 失效
    技术用于高性能埋地接触和钨硅化合物门集成

    公开(公告)号：US5998269A

    公开(公告)日：1999-12-07

    申请号：US35139

    申请日：1998-03-05

    Applicant: Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

    Inventor： Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

    IPC: H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8244 ,  H01L21/3215 ,  H01L21/335 ,  H01L21/74

    CPC classification number: H01L27/11 ,  H01L21/28512 ,  H01L21/76895 ,  H01L29/66545

    Abstract: A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. The polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact. A refractory metal layer is deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines and planarized to form polycide gate electrodes and interconnection lines. The dielectric material layer is removed. An oxide layer is deposited and anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

    Abstract translation: 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，其中它们不被掩模覆盖以形成多晶硅栅电极和互连线，其中间隙留在栅电极和互连线之间。 介电材料层沉积在半导体衬底上以填补间隙。 去除硬掩模层。 多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 植入离子以形成埋入的接触。 沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的难熔金属层并且被平坦化以形成多晶硅栅极电极和互连线。 去除介电材料层。 沉积氧化物层并各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

    Semiconductor devices and methods for fabricating the same
    17.
    发明授权
    Semiconductor devices and methods for fabricating the same 有权
    半导体器件及其制造方法

    公开(公告)号：US08012836B2

    公开(公告)日：2011-09-06

    申请号：US11528405

    申请日：2006-09-28

    Applicant: Kuo-Chyuan Tzeng ,  Jian-Yu Shen ,  Kuo-Chi Tu ,  Kuo-Ching Huang ,  Chin-Yang Chang

    Inventor： Kuo-Chyuan Tzeng ,  Jian-Yu Shen ,  Kuo-Chi Tu ,  Kuo-Ching Huang ,  Chin-Yang Chang

    IPC: H01L27/108 ,  H01L21/8242

    CPC classification number: H01L27/10894

    Abstract: Semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device comprises a substrate with a plurality of isolation structures formed therein, defining first and second areas over the substrate. A transistor is formed on a portion of the substrate in the first and second areas, respectively, wherein the transistor in the second area is formed with merely a pocket doping region in the substrate adjacent to a drain region thereof. A first dielectric layer is formed over the substrate, covering the transistor formed in the first and second areas. A plurality of first contact plugs is formed through the first dielectric layer, electrically connecting a source region and a drain region of the transistor in the second area, respectively. A second dielectric layer is formed over the first dielectric layer with a capacitor formed therein, wherein the capacitor electrically connects one of the first contact plugs.

    Abstract translation: 提供半导体器件及其制造方法。 半导体器件的示例性实施例包括在其中形成有多个隔离结构的衬底，其在衬底上限定第一和第二区域。 晶体管分别形成在第一和第二区域中的衬底的一部分上，其中第二区域中的晶体管仅在与衬底的漏极区相邻的衬底中仅形成一个凹坑掺杂区域。 第一电介质层形成在衬底上，覆盖形成在第一和第二区域中的晶体管。 通过第一介电层形成多个第一接触插塞，分别在第二区域中电连接晶体管的源极区域和漏极区域。 在第一电介质层上形成第二电介质层，其中形成有电容器，其中电容器电连接第一接触插塞之一。

    Securing device
    20.
    发明授权
    Securing device 失效
    固定装置

    公开(公告)号：US06909085B2

    公开(公告)日：2005-06-21

    申请号：US10456885

    申请日：2003-06-06

    Applicant: Kuo-Ching Huang

    Inventor： Kuo-Ching Huang

    IPC: H04N1/028 ,  H04N1/03 ,  H04N1/19 ,  H01J40/14 ,  H01J5/02

    CPC classification number: H04N1/03 ,  H04N2201/02456 ,  H04N2201/02474 ,  H04N2201/02485

    Abstract: A securing device includes a sustaining member, a plurality of threaded holes, and a plurality of screws. The sustaining member includes a clamped portion and a securing portion extending from the clamped portion. The clamped portion is interfaced between the photoelectric conversion device and the carriage module housing. The thickness of the clamped portion is even enough to keep the distance between the photoelectric conversion device and the carriage module housing constant, thereby assuring that the photoelectric conversion device is orthogonal to the central line of a lens in the carriage module housing. The securing portion is flexible so as to facilitate the assembling operation of the circuit board, the photoelectric conversion device and the carriage module housing by way of the threaded holes and screws.

    Abstract translation: 固定装置包括支撑构件，多个螺纹孔和多个螺钉。 保持构件包括夹紧部分和从夹紧部分延伸的固定部分。 夹持部分接合在光电转换装置和支架模块壳体之间。 夹持部分的厚度足以使光电转换装置和滑架模块壳体之间的距离恒定，从而确保光电转换装置与托架模块壳体中的透镜的中心线正交。 固定部分是柔性的，以便于通过螺纹孔和螺钉使电路板，光电转换装置和滑架模块壳体的组装操作。

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