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公开(公告)号:US20120049389A1
公开(公告)日:2012-03-01
申请号:US12874204
申请日:2010-09-01
申请人: Chetan Verma , Shailesh Kumar , Meng Kong Lye
发明人: Chetan Verma , Shailesh Kumar , Meng Kong Lye
IPC分类号: H01L23/488
CPC分类号: H01L24/06 , H01L22/32 , H01L24/05 , H01L2224/04042 , H01L2224/05644 , H01L2224/05647 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/181 , H01L2924/00014 , H01L2924/00
摘要: A semiconductor die has rows of bond pads along the edges of a major surface. The corners of the die are designated as keep out areas, with design layout rules prohibiting a probe-able bond pad from being placed in the keep out areas so that a minimum distance may be maintained between distal ends of adjacent rows of bond pads (i.e., bond pads along adjacent edges). The bond pads of each row have IO pad areas that are aligned with each other and IO probe areas that are aligned with each other. A generally L-shaped bond pad includes a first, vertical part that extends inwardly from an edge of the semiconductor die and a second, horizontal part connected to the vertical part. The L-shaped bond pad may be placed between a last bond pad in a row and a corner keep out area, and the second part of the L-shaped bond pad extends into the corner keep out area. The first part has an IO pad area that is in alignment with the IO pad areas of the other bond pads in the same row, and the second part has an IO probe area that is in alignment with the IO probe areas of the bond pads in the adjacent row. The L-shaped bond pad does not violate design rules even though a part of the pad extends into the corner keep out area.
摘要翻译: 半导体管芯沿着主表面的边缘具有一排接合焊盘。 模具的角被指定为保留区域,其设计布局规则禁止可探测的焊盘放置在保留区域中,使得可以在相邻排的焊盘的末端之间保持最小距离(即 ,沿着相邻边缘的接合垫)。 每行的接合焊盘具有彼此对准的IO焊盘区域和彼此对准的IO探针区域。 大致L形接合焊盘包括从半导体管芯的边缘向内延伸的第一垂直部分和连接到垂直部分的第二水平部分。 L形接合焊盘可以放置在一行中的最后接合焊盘和拐角保持区域之间,并且L形接合焊盘的第二部分延伸到角落保持区域中。 第一部分具有与同一行中的其它接合焊盘的IO焊盘区域对准的IO焊盘区域,并且第二部分具有与焊盘的IO探针区域对准的IO探针区域 相邻行。 即使垫的一部分延伸到角落保持区域,L形接合垫也不违反设计规则。
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公开(公告)号:US08242613B2
公开(公告)日:2012-08-14
申请号:US12874204
申请日:2010-09-01
申请人: Chetan Verma , Shailesh Kumar , Meng Kong Lye
发明人: Chetan Verma , Shailesh Kumar , Meng Kong Lye
IPC分类号: H01L23/488 , H01L23/485 , H01L21/768 , H01L23/48
CPC分类号: H01L24/06 , H01L22/32 , H01L24/05 , H01L2224/04042 , H01L2224/05644 , H01L2224/05647 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/181 , H01L2924/00014 , H01L2924/00
摘要: A semiconductor die has rows of bond pads along the edges of a major surface. The corners of the die are designated as keep out areas, with design layout rules prohibiting a probe-able bond pad from being placed in the keep out areas so that a minimum distance may be maintained between distal ends of adjacent rows of bond pads (i.e., bond pads along adjacent edges). The bond pads of each row have IO pad areas that are aligned with each other and IO probe areas that are aligned with each other. A generally L-shaped bond pad includes a first, vertical part that extends inwardly from an edge of the semiconductor die and a second, horizontal part connected to the vertical part. The L-shaped bond pad may be placed between a last bond pad in a row and a corner keep out area, and the second part of the L-shaped bond pad extends into the corner keep out area. The first part has an IO pad area that is in alignment with the IO pad areas of the other bond pads in the same row, and the second part has an IO probe area that is in alignment with the IO probe areas of the bond pads in the adjacent row. The L-shaped bond pad does not violate design rules even though a part of the pad extends into the corner keep out area.
摘要翻译: 半导体管芯沿着主表面的边缘具有一排接合焊盘。 模具的角被指定为保留区域,其设计布局规则禁止可探测的焊盘放置在保留区域中,使得可以在相邻排的焊盘的末端之间保持最小距离(即 ,沿着相邻边缘的接合垫)。 每行的接合焊盘具有彼此对准的IO焊盘区域和彼此对准的IO探针区域。 大致L形接合焊盘包括从半导体管芯的边缘向内延伸的第一垂直部分和连接到垂直部分的第二水平部分。 L形接合焊盘可以放置在一行中的最后接合焊盘和拐角保持区域之间,并且L形接合焊盘的第二部分延伸到角落保持区域中。 第一部分具有与同一行中的其它接合焊盘的IO焊盘区域对准的IO焊盘区域,并且第二部分具有与焊盘的IO探针区域对准的IO探针区域 相邻行。 即使垫的一部分延伸到角落保持区域,L形接合垫也不违反设计规则。
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公开(公告)号:US20160233183A1
公开(公告)日:2016-08-11
申请号:US14620155
申请日:2015-02-11
申请人: Shailesh Kumar , Vikas Garg , Meng Kong Lye
发明人: Shailesh Kumar , Vikas Garg , Meng Kong Lye
IPC分类号: H01L23/00
CPC分类号: H01L24/06 , H01L23/3171 , H01L24/02 , H01L24/05 , H01L2224/0235 , H01L2224/02375 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05567 , H01L2224/0603 , H01L2224/06051 , H01L2224/06131 , H01L2224/06135 , H01L2224/06138 , H01L2224/06139 , H01L2224/06179 , H01L2924/00012
摘要: An integrated circuit (IC) die has side input/output (IO) pads located along each side of the die interior. Each die corner has a corner IO pad. The side IO pads adjacent to the corner IO pads have shortened passivation regions in the top metal layer (TML) that define TML access regions. TML traces run through the TML access regions to connect the corner IO pads to the die interior. Providing corner IO pads enables an IC die to have up to four more IO pads than a comparable conventional IC die that does not have any corner IO pads, or an IC die to have the same number of IO pads within a smaller overall footprint.
摘要翻译: 集成电路(IC)管芯具有位于管芯内部的每一侧的侧面输入/输出(IO)焊盘。 每个模具角都有一个角落的IO垫。 靠近角IO垫的侧IO垫具有限定TML访问区域的顶层金属层(TML)中的钝化区域缩短。 TML轨迹通过TML访问区域将角IO垫连接到模具内部。 提供拐角IO垫使IC芯片能够具有比不具有任何拐角IO垫的可比较的常规IC芯片多达四个IO垫,或IC芯片在更小的总体占地面积内具有相同数量的IO焊盘。
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公开(公告)号:US09196578B1
公开(公告)日:2015-11-24
申请号:US14459337
申请日:2014-08-14
申请人: Sheau Mei Lim , Meng Kong Lye , Pei Fan Tong
发明人: Sheau Mei Lim , Meng Kong Lye , Pei Fan Tong
IPC分类号: H01L23/495
CPC分类号: H01L23/49575 , H01L23/49503 , H01L23/49541 , H01L2224/05554 , H01L2224/49113 , H01L2224/49171
摘要: A semiconductor package has multiple dies and an interior power bar that extends within an interior space formed within the die flag between the dies. The bond pads located on the interior side of each die are wire-bonded to the interior power bar. Some embodiments may have more than two dies and/or more than one interior power bar between each pair of adjacent dies.
摘要翻译: 半导体封装具有多个管芯和内部电源杆,其在形成在管芯之间的管芯标记内的内部空间内延伸。 位于每个模具的内侧的接合焊盘被引线接合到内部电源杆。 一些实施例可以在每对相邻的模具之间具有多于两个的模具和/或多于一个的内部功率杆。
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公开(公告)号:US09147656B1
公开(公告)日:2015-09-29
申请号:US14328711
申请日:2014-07-11
申请人: Sumit Varshney , Rishi Bhooshan , Meng Kong Lye , Chetan Verma
发明人: Sumit Varshney , Rishi Bhooshan , Meng Kong Lye , Chetan Verma
IPC分类号: H01L23/495 , H01L23/552 , H01L23/522
CPC分类号: H01L23/49558 , H01L23/49541 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/04042 , H01L2224/32245 , H01L2224/48247 , H01L2224/48257 , H01L2224/73265 , H01L2924/00014 , H01L2924/14 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A shielding structure for use with semiconductor devices. The shielding structure has a base with fingers that are sized and shaped to extend within the space between pairs of adjacent leads. The base extends within the space between the die flag and the leads. The shielding structure is further connected to one of the grounded leads.
摘要翻译: 一种用于半导体器件的屏蔽结构。 屏蔽结构具有带指状物的基座,其尺寸和形状被设计成在相邻引线对之间的空间内延伸。 基座在芯片标记和引线之间的空间内延伸。 屏蔽结构进一步连接到一个接地引线。
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公开(公告)号:US09633959B2
公开(公告)日:2017-04-25
申请号:US14620155
申请日:2015-02-11
申请人: Shailesh Kumar , Vikas Garg , Meng Kong Lye
发明人: Shailesh Kumar , Vikas Garg , Meng Kong Lye
CPC分类号: H01L24/06 , H01L23/3171 , H01L24/02 , H01L24/05 , H01L2224/0235 , H01L2224/02375 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05567 , H01L2224/0603 , H01L2224/06051 , H01L2224/06131 , H01L2224/06135 , H01L2224/06138 , H01L2224/06139 , H01L2224/06179 , H01L2924/00012
摘要: An integrated circuit (IC) die has side input/output (IO) pads located along each side of the die interior. Each die corner has a corner IO pad. The side IO pads adjacent to the corner IO pads have shortened passivation regions in the top metal layer (TML) that define TML access regions. TML traces run through the TML access regions to connect the corner IO pads to the die interior. Providing corner IO pads enables an IC die to have up to four more IO pads than a comparable conventional IC die that does not have any corner IO pads, or an IC die to have the same number of IO pads within a smaller overall footprint.
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公开(公告)号:US09177834B2
公开(公告)日:2015-11-03
申请号:US14184672
申请日:2014-02-19
申请人: Chee Seng Foong , Meng Kong Lye , Lan Chu Tan , Seng Kiong Teng
发明人: Chee Seng Foong , Meng Kong Lye , Lan Chu Tan , Seng Kiong Teng
IPC分类号: H01L23/495 , H01L21/56 , H01L23/31 , H01L23/00
CPC分类号: H01L21/56 , H01L23/3107 , H01L23/49541 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/72 , H01L24/73 , H01L24/85 , H01L2224/27334 , H01L2224/2919 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45664 , H01L2224/48245 , H01L2224/732 , H01L2224/73265 , H01L2224/85 , H01L2224/85411 , H01L2224/85424 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/85464 , H01L2924/00014 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/0665 , H01L2224/48 , H01L2224/72
摘要: A semiconductor device includes a semiconductor die encapsulated in a package casing and having four main side walls each oriented generally parallel with one of first or second orthogonal directions. Signal leads are electrically coupled to the die and each has an exposed portion that extends from one of the main side walls parallel with one of the first or second directions. One or more power bars are electrically coupled to the die and each has at least one power bar lead extending at a non-zero angle with respect to the first and second directions. The power bars and associated power bar leads are electrically isolated from the signal leads. One or more tie bars extends at a generally non-zero angle with respect to the first and second directions and is electrically isolated from the signal leads and the power bars and associated power bar leads.
摘要翻译: 半导体器件包括封装在封装壳体中并具有四个主侧壁的半导体管芯,每个主侧壁大致平行于第一或第二正交方向之一。 信号引线电耦合到管芯,并且每个具有从主侧壁中的一个平行于第一或第二方向之一延伸的暴露部分。 一个或多个电源杆电耦合到管芯,并且每个具有至少一个相对于第一和第二方向以非零角度延伸的电源杆引线。 电源条和相关的电源条引线与信号引线电隔离。 一个或多个连接杆相对于第一和第二方向以大致非零的角度延伸,并且与信号引线和功率条以及相关联的功率条引线电隔离。
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公开(公告)号:US09165869B1
公开(公告)日:2015-10-20
申请号:US14328713
申请日:2014-07-11
申请人: Soo Choong Chee , Meng Kong Lye , Wai Keong Wong
发明人: Soo Choong Chee , Meng Kong Lye , Wai Keong Wong
IPC分类号: H01L23/495
CPC分类号: H01L23/49551 , H01L23/49541 , H01L24/48 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A lead frame for a semiconductor device has a die flag and leads that surround the die flag. In order to decrease the distance or spacing between inner lead ends and the die flag, which allows for short bond wires for connecting the inner lead ends to a die mounted on the die flag, at least some of the leads are twisted along their lengths to be angled with respect to a die-flag plane. The pitch between such twisted leads can be reduced without resulting in physical contact between adjacent leads, enabling the leads to extend further towards the die flag.
摘要翻译: 用于半导体器件的引线框具有裸片标记和包围裸片标记的引线。 为了减小内引线端和芯片标记之间的距离或间距,这允许用于将内引线端连接到安装在管芯标记上的管芯的短接合线,至少一些引线沿着它们的长度被扭曲到 相对于模具标志平面成角度。 可以减小这种扭绞引线之间的间距,而不会导致相邻引线之间的物理接触,使得引线能够进一步向着模具标记延伸。
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公开(公告)号:US20150235924A1
公开(公告)日:2015-08-20
申请号:US14184672
申请日:2014-02-19
申请人: Chee Seng Foong , Meng Kong Lye , Lan Chu Tan , Seng Kiong Teng
发明人: Chee Seng Foong , Meng Kong Lye , Lan Chu Tan , Seng Kiong Teng
IPC分类号: H01L23/495 , H01L23/00 , H01L21/56 , H01L23/31
CPC分类号: H01L21/56 , H01L23/3107 , H01L23/49541 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/72 , H01L24/73 , H01L24/85 , H01L2224/27334 , H01L2224/2919 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45664 , H01L2224/48245 , H01L2224/732 , H01L2224/73265 , H01L2224/85 , H01L2224/85411 , H01L2224/85424 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/85464 , H01L2924/00014 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/0665 , H01L2224/48 , H01L2224/72
摘要: A semiconductor device includes a semiconductor die encapsulated in a package casing and having four main side walls each oriented generally parallel with one of first or second orthogonal directions. Signal leads are electrically coupled to the die and each has an exposed portion that extends from one of the main side walls parallel with one of the first or second directions. One or more power bars are electrically coupled to the die and each has at least one power bar lead extending at a non-zero angle with respect to the first and second directions. The power bars and associated power bar leads are electrically isolated from the signal leads. One or more tie bars extends at a generally non-zero angle with respect to the first and second directions and is electrically isolated from the signal leads and the power bars and associated power bar leads.
摘要翻译: 半导体器件包括封装在封装壳体中并具有四个主侧壁的半导体管芯,每个主侧壁大致平行于第一或第二正交方向之一。 信号引线电耦合到管芯,并且每个具有从主侧壁中的一个平行于第一或第二方向之一延伸的暴露部分。 一个或多个电源杆电耦合到管芯,并且每个具有至少一个相对于第一和第二方向以非零角度延伸的电源杆引线。 电源条和相关的电源条引线与信号引线电隔离。 一个或多个连接杆相对于第一和第二方向以大致非零的角度延伸,并且与信号引线和功率条以及相关联的功率条引线电隔离。
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