-
公开(公告)号：US11668874B1
公开(公告)日：2023-06-06
申请号：US17700077
申请日：2022-03-21
Applicant: XILINX, INC.
Inventor： Zhaoyin Daniel Wu , Chuan Xie , Mayank Raj , Parag Upadhyaya
CPC classification number: G02B6/12016 , G02B6/2938 , G02B6/29338 , G02B6/29395
Abstract: Disclosed herein is an optical filter configured for wavelength division and multiplexing capable of transmitting and receiving signals. The optical filter includes an optical waveguide configured to receive at an input multiple signals with different wavelengths. The optical filter includes a plurality of channels coupled at different locations along a length of the optical waveguide. Each of the plurality of channels is configured to transmit a respective one of the multiple signals. A number of ring filter stages in a first channel of the plurality of channels that is closer to the input of the optical waveguide is greater than a second channel in the plurality of channels further away from the input of the optical waveguide.
-
公开(公告)号：US11637528B1
公开(公告)日：2023-04-25
申请号：US17689748
申请日：2022-03-08
Applicant: XILINX, INC.
Inventor： Adebabay M. Bekele , Parag Upadhyaya
Abstract: Transformer based voltage controlled oscillator circuitry for phase-locked loop circuitry includes upper band circuitry and lower band circuitry. The upper band circuitry operates in a first frequency range and includes a first capacitor array having a variable capacitance. The lower band circuitry operates in a second frequency range and includes a second capacitor array having a variable capacitance. The first frequency range higher than the second frequency range. In a first operating mode, the first capacitor array has a first capacitance value and the second capacitor array has a second capacitance value. In a second operating mode, the second capacitor array has a third capacitance value different than the second capacitance value.
-
公开(公告)号：US11277144B1
公开(公告)日：2022-03-15
申请号：US16840533
申请日：2020-04-06
Applicant: Xilinx, Inc.
Inventor： Junho Cho , Parag Upadhyaya
Abstract: An apparatus for reducing or removing a direct current (DC) offset voltage from one or more analog signals is disclosed. An analog signal may be received by an integrator. The integrator may integrate the analog signal to determine a DC offset error signal. The apparatus may integrate, invert, and amplify the DC offset error signal to provide an analog correction signal. The analog correction signal may be inverted and subtracted from the analog signal. In some implementations, the apparatus may include multiple, independent circuits to reduce or remove DC offset voltages from differential signals.
-
公开(公告)号：US10715153B1
公开(公告)日：2020-07-14
申请号：US16517103
申请日：2019-07-19
Applicant: XILINX, INC.
Inventor： Adebabay M. Bekele , Parag Upadhyaya , Didem Z. Turker Melek , Jing Jing
Abstract: Apparatus and associated methods relate to automatically generating a data structure representation of an on-chip inductive-capacitive (LC) tank circuit by determining parasitic inductances in each of the segments of conductive paths that connect a main inductor to one or more selectable VCO components such as capacitors and varactors, for example. In an illustrative example, one or more of the selectable VCO components may be arranged, when selected, to form a parallel resonant LC tank with the main inductor. A method may include defining nodes ai terminating each of the segments along the conductive paths between the main inductor terminals and a drive circuit. By modelling the paths as multi-port inductors and transformers, resonant frequency of the VCO may be more accurately predicted by simulation.
-
公开(公告)号：US09774315B2
公开(公告)日：2017-09-26
申请号：US14933346
申请日：2015-11-05
Applicant: Xilinx, Inc.
Inventor： Jinyung Namkoong , Wenfeng Zhang , Parag Upadhyaya
CPC classification number: H03K3/01 , H03K19/017527
Abstract: Methods and apparatus are described for a differential active inductor load for inductive peaking in which cross-coupled capacitive elements are used to cancel out, or at least reduce, the limiting effect of the gate-to-drain capacitance (Cgd) of transistors in the active inductor load. The cross-coupled capacitive elements extend the range over which the active inductor load behaves inductively and increase the quality factor (Q) of each active inductor. Therefore, the achievable inductive peaking of the load is significantly increased, which leads to providing larger signal swing across the load for a given power or, alternatively, lower power for a given signal swing.
-
Patent Agency Ranking
公开(公告)号：US09614537B1
公开(公告)日：2017-04-04
申请号：US15093655
申请日：2016-04-07
Applicant: Xilinx, Inc.
Inventor： Romesh Kumar Nandwana , Parag Upadhyaya
CPC classification number: H03L7/24 , H03L7/0805 , H03L7/081 , H03L2207/06 , H03L2207/50
Abstract: An example clock generator circuit includes a fractional reference generator configured to generate a reference clock in response to a base reference clock and a phase error signal, the reference clock having a frequency that is a rational multiple of a frequency of the base reference clock. The clock generator circuit includes a digitally controlled delay line (DCDL) that delays the reference clock based on a first control code, and a pulse generator configured to generate pulses based on the delayed reference clock. The clock generator circuit includes a digitally controlled oscillator (DCO) configured to generate an output clock based on a second control code, the DCO including an injection input coupled to the pulse generator to receive the pulses. The clock generator circuit includes a phase detector configured to compare the output clock and the reference clock and generate the phase error signal, and a control circuit configured to generate the first and second control codes based on the phase error signal.
-
公开(公告)号：US09559792B1
公开(公告)日：2017-01-31
申请号：US14841212
申请日：2015-08-31
Applicant: Xilinx, Inc.
Inventor： Hesam Amir-Aslanzadeh , Parag Upadhyaya
CPC classification number: H04B17/12 , H04L27/2631 , H04L27/362 , H04L2027/0057
Abstract: An apparatus, and method therefor, relate generally to broadband IQ generation. In this apparatus, related generally to broadband in-phase and quadrature phase (“IQ”) generation, a divider circuit and a polyphase filter circuit are configured for receiving an oscillator output. The polyphase filter circuit is configured for polyphase filtering the oscillator output into a first quadrature output. The divider circuit is configured for dividing the oscillator output into a second quadrature output. A multiplexer circuit is coupled to the divider circuit and the polyphase filter circuit and configured for selecting either the first quadrature output or the second quadrature output as an IQ output based on a bandwidth of the oscillator output.
Abstract translation: 一种装置及其方法一般涉及宽带IQ生成。 在该装置中，通常涉及宽带同相和正交相位（“IQ”）产生，分频器电路和多相滤波器电路被配置用于接收振荡器输出。 多相滤波器电路被配置为将振荡器输出多相滤波成第一正交输出。 分频器电路被配置为将振荡器输出分成第二正交输出。 多路复用器电路耦合到分频器电路和多相滤波器电路，并且被配置为基于振荡器输出的带宽来选择第一正交输出或第二正交输出作为IQ输出。
-
18.发明授权Circuits for and methods of generating a divided clock signal with a configurable phase offset 有权用于生成具有可配置相位偏移的分频时钟信号的电路和方法公开(公告)号：US09553592B1
公开(公告)日：2017-01-24
申请号：US14639197
申请日：2015-03-05
Applicant: Xilinx, Inc.
Inventor： Aman Sewani , Fu-Tai An , Parag Upadhyaya
Abstract: A circuit for generating a divided clock signal with a configurable phase offset comprises a first latch circuit adapted to receive a clock signal to be divided; a second latch coupled to an output of the first latch circuit and generating a divided output clock signal; and an initialization circuit coupled to the first latch circuit and the second latch circuit, the initialization circuit coupled to receive an initialization signal. The initialization signal determines a phase offset between the divided output clock signal and the clock signal to be divided. A method of generating a divided clock signal is also described.
Abstract translation: 用于产生具有可配置相位偏移的分频时钟信号的电路包括适于接收待分频的时钟信号的第一锁存电路; 第二锁存器，耦合到所述第一锁存电路的输出并产生分频的输出时钟信号; 以及耦合到所述第一锁存电路和所述第二锁存电路的初始化电路，所述初始化电路被耦合以接收初始化信号。 初始化信号决定分割后的输出时钟信号与待分割的时钟信号之间的相位偏移。 还描述了产生分频时钟信号的方法。
-
19.发明授权公开(公告)号：US09214941B2
公开(公告)日：2015-12-15
申请号：US14014879
申请日：2013-08-30
Applicant: Xilinx, Inc.
Inventor： Aman Sewani , Parag Upadhyaya
IPC: H03K19/0185 , H03K19/177
CPC classification number: H03K19/018521 , H03K19/17744 , H03K19/1778 , H03K19/17788
Abstract: An input/output circuit implemented in an integrated circuit is described. The input/output circuit comprises an input/output pad and a voltage control circuit coupled to the input/output pad. The voltage control circuit sets a voltage at the input/output pad at a first voltage when the input/output pad is implemented as an input pad and at a second voltage when the input/output pad is implemented as an output pad. Methods of implementing input/output circuits in an integrated circuit are also described.
Abstract translation: 描述了在集成电路中实现的输入/输出电路。 输入/输出电路包括输入/输出焊盘和耦合到输入/输出焊盘的电压控制电路。 当输入/输出焊盘被实现为输入焊盘时，电压控制电路以第一电压设置输入/输出焊盘处的电压，并且当输入/输出焊盘被实现为输出焊盘时，电压控制电路将第二电压设置为第一电压。 还描述了在集成电路中实现输入/输出电路的方法。
-
公开(公告)号：US20250088287A1
公开(公告)日：2025-03-13
申请号：US18463078
申请日：2023-09-07
Applicant: Xilinx, Inc.
Inventor： Wenfeng Zhang , Parag Upadhyaya
Abstract: A transceiver circuit is disclosed. The transceiver circuit includes a transmitter driver circuit configured to drive a transmit antenna. The transceiver circuit also includes a receiver circuit configured to generate digital signals based on received signals. The transceiver circuit also includes a loopback data path circuit electrically connected to the transmitter driver circuit and to the receiver circuit, where the loopback data path circuit is configured to conditionally provide signals from the transmitter driver circuit to the receiver circuit according to one or more control signals. The transceiver circuit also includes a controller configured to generate the control signals.
-
-
-
-
-
-
-
-
-
Search Results
60
records
(took 0.018 seconds)
