公开(公告)号：US09209316B2

公开(公告)日：2015-12-08

申请号：US13421389

申请日：2012-03-15

申请人： Chih-Chieh Cheng ,  Cheng-Hsien Cheng ,  Wen-Jer Tsai

发明人： Chih-Chieh Cheng ,  Cheng-Hsien Cheng ,  Wen-Jer Tsai

IPC分类号： H01L27/115 ,  H01L29/792 ,  G11C11/56 ,  G11C16/04

CPC分类号： H01L29/792 ,  G11C11/5621 ,  G11C16/0466 ,  H01L27/11521 ,  H01L27/11568

摘要： A read only memory including a substrate, a source region and a drain region, a charge storage structure, a gate, and a local extreme doping region is provided. The source region and the drain region are disposed in the substrate, the charge storage structure is located on the substrate between the source region and the drain region, and the gate is configured on the charge storage structure. The local extreme doping region is located in the substrate between the source region and the drain region and includes a low doping concentration region and at least one high doping concentration region. The high doping concentration region is disposed between the low doping concentration region and one of the source region and the drain region, and a doping concentration of the high doping concentration region is three times or more than three times a doping concentration of the low doping concentration region.

摘要翻译： 提供了包括基板，源极区和漏极区，电荷存储结构，栅极和局部极化掺杂区域的只读存储器。 源极区域和漏极区域设置在衬底中，电荷存储结构位于源极区域和漏极区域之间的衬底上，并且栅极被配置在电荷存储结构上。 局部极掺杂区位于源区和漏区之间的衬底中，并且包括低掺杂浓度区和至少一个高掺杂浓度区。 高掺杂浓度区域设置在低掺杂浓度区域和源极区域和漏极区域之一中，并且高掺杂浓度区域的掺杂浓度是低掺杂浓度的掺杂浓度的三倍或更多倍 地区。

公开(公告)号：US08947939B2

公开(公告)日：2015-02-03

申请号：US12898979

申请日：2010-10-06

申请人： Ping-Hung Tsai ,  Jyun-Siang Huang ,  Wen-Jer Tsai

发明人： Ping-Hung Tsai ,  Jyun-Siang Huang ,  Wen-Jer Tsai

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3427

摘要： A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection. The program operation is based on metering a flow of carriers between a first semiconductor body region on a first side of the selected cell in the NAND string and a second semiconductor body region on a second side of the selected cell. A program potential higher than a hot carrier injection barrier level is applied to the selected cell, and then the drain to source voltage across the selected cell and the flow of carriers in the selected cell reach a level sufficient to support hot carrier injection, which is controlled by a switch cell adjacent the selected cell.

摘要翻译： 存储器件包括串联布置在半导体本体中的多个存储单元，例如具有多个字线的NAND串。 选择的存储单元通过热载流子注入进行编程。 编程操作基于在NAND串中所选择的单元的第一侧上的第一半导体主体区域与所选择的单元的第二侧上的第二半导体本体区域之间计量载流子流。 将高于热载流子注入势垒级的程序电位施加到所选择的单元，然后跨越所选择的单元的漏极到源极电压，并且所选择的单元中的载流子流达到足以支持热载流子注入的水平， 由与所选择的单元相邻的开关单元控制。

公开(公告)号：US08665652B2

公开(公告)日：2014-03-04

申请号：US13168554

申请日：2011-06-24

申请人： Jyun-Siang Huang ,  Wen-Jer Tsai ,  Ping-Hung Tsai

发明人： Jyun-Siang Huang ,  Wen-Jer Tsai ,  Ping-Hung Tsai

IPC分类号： G11C11/34

CPC分类号： G11C16/16

摘要： A method for erasing a memory array is provided. The memory array comprises a plurality of memory cell strings, and each of the memory cell strings comprises a plurality of memory cells connected to a plurality of word lines. The method for erasing the memory array includes the following steps. A first voltage is applied to a substrate of the memory array. A second voltage is applied to a word line of a selected memory cell, and a plurality of passing voltages are applied to other word lines. And, a third voltage and a fourth voltage are respectively applied to a first source/drain region and a second source/drain region of the selected memory cell, so that a band to band (BTB) hot hole injecting method is induced to erase the specific memory cell, wherein the third voltage is not equal to the fourth voltage.

摘要翻译： 提供了一种擦除存储器阵列的方法。 存储器阵列包括多个存储单元串，并且每个存储单元串包括连接到多个字线的多个存储单元。 擦除存储器阵列的方法包括以下步骤。 将第一电压施加到存储器阵列的衬底。 第二电压被施加到所选存储单元的字线，并且多个通过电压被施加到其它字线。 并且，将第三电压和第四电压分别施加到所选择的存储单元的第一源极/漏极区域和第二源极/漏极区域，使得引入带对（BTB）热空穴注入方法来擦除 特定存储单元，其中第三电压不等于第四电压。

公开(公告)号：US08520439B2

公开(公告)日：2013-08-27

申请号：US13346432

申请日：2012-01-09

申请人： Wen-Jer Tsai ,  Ping-Hung Tsai ,  Jyun-Siang Huang

发明人： Wen-Jer Tsai ,  Ping-Hung Tsai ,  Jyun-Siang Huang

IPC分类号： G11C16/12

CPC分类号： G11C16/3468 ,  G11C16/24

摘要： A method for programming a memory array is provided. The memory array includes a memory cell string composed of a first transistor, a plurality of memory cells and a second transistor connected in series, and the method for programming the memory array includes following steps. In a setup phase, a switching memory cell in the memory cells is turned off, and a first voltage and a second voltage are applied to a first source/drain and a second source/drain of the switching memory cell. In a programming phase, a bit line connected to the memory cell string is floating, and a ramp signal is provided to a word line electrically connected to the switching memory cell.

摘要翻译： 提供了一种用于编程存储器阵列的方法。 存储器阵列包括由第一晶体管，多个存储单元和串联连接的第二晶体管组成的存储单元串，并且存储器阵列的编程方法包括以下步骤。 在设置阶段，关闭存储单元中的开关存储单元，并将第一电压和第二电压施加到开关存储单元的第一源极/漏极和第二源极/漏极。 在编程阶段，连接到存储单元串的位线是浮置的，并且斜坡信号被提供给电连接到开关存储单元的字线。

公开(公告)号：US20130105882A1

公开(公告)日：2013-05-02

申请号：US13287728

申请日：2011-11-02

申请人： Jyun-Siang Huang ,  Wen-Jer Tsai ,  Shih-Guei Yan

发明人： Jyun-Siang Huang ,  Wen-Jer Tsai ,  Shih-Guei Yan

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42332 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A memory structure having a memory cell including a first dielectric layer, a gate, a semiconductor layer, a first doped region, a second doped region and a charge storage layer is provided. The first dielectric layer is on the substrate. The gate includes a base portion on the first dielectric layer and a protruding portion disposed on the base portion and partially exposing the base portion. The semiconductor layer is conformally disposed on the gate, and includes a top portion over the protruding portion, a bottom portion over the base portion exposed by the protruding portion and a side portion located at a sidewall of the protruding portion and connecting the top and bottom portions. The first and second doped regions are respectively in the top and bottom portions. The side portion serves as a channel region. The charge storage layer is between the gate and the semiconductor layer.

摘要翻译： 提供了具有包括第一介电层，栅极，半导体层，第一掺杂区域，第二掺杂区域和电荷存储层的存储单元的存储器结构。 第一介电层位于基板上。 所述栅极包括在所述第一介电层上的基部和设置在所述基部上的部分露出所述基部的突出部。 所述半导体层保形地设置在所述栅极上，并且包括在所述突出部分之上的顶部，所述基部上的由所述突出部分露出的底部和位于所述突出部分的侧壁处的侧部，并且将所述顶部和底部 部分。 第一和第二掺杂区分别位于顶部和底部。 侧部用作沟道区域。 电荷存储层位于栅极和半导体层之间。

公开(公告)号：US20130088920A1

公开(公告)日：2013-04-11

申请号：US13271161

申请日：2011-10-11

申请人： JYUN-SIANG HUANG ,  Wen-Jer Tsai ,  Ping-Hung Tsai

发明人： JYUN-SIANG HUANG ,  Wen-Jer Tsai ,  Ping-Hung Tsai

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/12

摘要： A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection. The program operation is based on metering a flow of carriers between a first semiconductor body region on a first side of the selected cell in the NAND string and a second semiconductor body region on a second side of the selected cell. A program potential higher than a hot carrier injection barrier level is applied to the selected cell, and then the drain to source voltage across the selected cell and the flow of carriers in the selected cell reach a level sufficient to support hot carrier injection, which is controlled by a combination of a switch cell adjacent the selected cell and modulation of a source side voltage applied to the NAND string.

摘要翻译： 存储器件包括串联布置在半导体本体中的多个存储单元，例如具有多个字线的NAND串。 选择的存储单元通过热载流子注入进行编程。 编程操作基于在NAND串中所选择的单元的第一侧上的第一半导体主体区域与所选择的单元的第二侧上的第二半导体本体区域之间计量载流子流。 将高于热载流子注入势垒级的程序电位施加到所选择的单元，然后跨越所选择的单元的漏极到源极电压，并且所选择的单元中的载流子流达到足以支持热载流子注入的水平， 由与所选择的单元相邻的开关单元的组合以及施加到NAND串的源极侧电压的调制来控制。

公开(公告)号：US20120327721A1

公开(公告)日：2012-12-27

申请号：US13168554

申请日：2011-06-24

申请人： Jyun-Siang Huang ,  Wen-Jer Tsai ,  Ping-Hung Tsai

发明人： Jyun-Siang Huang ,  Wen-Jer Tsai ,  Ping-Hung Tsai

IPC分类号： G11C16/16

CPC分类号： G11C16/16

摘要： A method for erasing a memory array is provided. The memory array comprises a plurality of memory cell strings, and each of the memory cell strings comprises a plurality of memory cells connected to a plurality of word lines. The method for erasing the memory array includes the following steps. A first voltage is applied to a substrate of the memory array. A second voltage is applied to a word line of a selected memory cell, and a plurality of passing voltages are applied to other word lines. And, a third voltage and a fourth voltage are respectively applied to a first source/drain region and a second source/drain region of the selected memory cell, so that a band to band (BTB) hot hole injecting method is induced to erase the specific memory cell, wherein the third voltage is not equal to the fourth voltage.

摘要翻译： 提供了一种擦除存储器阵列的方法。 存储器阵列包括多个存储单元串，并且每个存储单元串包括连接到多个字线的多个存储单元。 擦除存储器阵列的方法包括以下步骤。 将第一电压施加到存储器阵列的衬底。 第二电压被施加到所选存储单元的字线，并且多个通过电压被施加到其它字线。 并且，将第三电压和第四电压分别施加到所选择的存储单元的第一源极/漏极区域和第二源极/漏极区域，使得引入带对（BTB）热空穴注入方法来擦除 特定存储单元，其中第三电压不等于第四电压。

公开(公告)号：US20120287724A1

公开(公告)日：2012-11-15

申请号：US13105276

申请日：2011-05-11

申请人： Ping-Hung Tsai ,  Jyun-Siang Huang ,  Wen-Jer Tsai

发明人： Ping-Hung Tsai ,  Jyun-Siang Huang ,  Wen-Jer Tsai

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/0433 ,  G11C16/32 ,  G11C16/3454

摘要： A method of programming a memory is provided. The memory has a first cell, having a first S/D region and a second S/D region shared with a second cell. The second cell has a third S/D region opposite to the second S/D region. When programming the first cell, a first voltage is applied to a control gate of the first cell, a second voltage is applied to a control gate of the second cell to slightly turn on a channel of the second cell, a third and a fourth voltage are respectively applied to the first and the third S/D regions, and the second S/D region is floating. A carrier flows from the third S/D region to the first S/D region, and is injected into a charge storage layer of the first cell by source-side injection.

摘要翻译： 提供了一种编程存储器的方法。 存储器具有第一单元，具有与第二单元共用的第一S / D区和第二S / D区。 第二单元具有与第二S / D区相反的第三S / D区。 当对第一单元进行编程时，第一电压被施加到第一单元的控制栅极，第二电压被施加到第二单元的控制栅极，以稍微导通第二单元的沟道，第三和第四电压 分别施加到第一和第三S / D区域，并且第二S / D区域是浮置的。 载体从第三S / D区流向第一S / D区，并通过源侧注入注入第一单元的电荷存储层。

公开(公告)号：US07864594B2

公开(公告)日：2011-01-04

申请号：US12250766

申请日：2008-10-14

申请人： Wen-Jer Tsai ,  Tien-Fan Ou ,  Jyun-Siang Huang

发明人： Wen-Jer Tsai ,  Tien-Fan Ou ,  Jyun-Siang Huang

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10

摘要： A memory apparatus, a controller, and a method thereof for programming non-volatile memory cells are provided. The memory apparatus includes a plurality of memory cells, wherein each memory cell shares a source/drain region with a neighboring memory cell. The method utilizes a compensation electron flow applied into a source/drain region between two memory cells to provide enough electron flow to program one of the two memory cells, even under the circumstances that the other memory cell has a greater threshold voltage, such that the dispersion of the programming speed of the memory cells is reduced.

摘要翻译： 提供了一种用于编程非易失性存储器单元的存储装置，控制器及其方法。 存储装置包括多个存储单元，其中每个存储单元与相邻的存储单元共享源/漏区。 该方法利用施加到两个存储单元之间的源极/漏极区域中的补偿电子流，以提供足够的电子流来编程两个存储器单元之一，即使在另一个存储单元具有较大的阈值电压的情况下， 存储器单元的编程速度的偏差减小。

公开(公告)号：US20100176437A1

公开(公告)日：2010-07-15

申请号：US12352947

申请日：2009-01-13

申请人： Jyun-Siang Huang ,  Wen-Jer Tsai ,  Tien-Fan Ou

发明人： Jyun-Siang Huang ,  Wen-Jer Tsai ,  Tien-Fan Ou

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/11565 ,  H01L29/4234 ,  H01L29/792

摘要： The invention provides a memory array. The memory array comprises a substrate, a plurality of word lines, a charge trapping structure, a plurality of trench channels and a plurality of bit lines. The word lines are located over the substrate and the word lines are parallel to each other. The charge trapping structure covers a surface of each of the word lines. The trench channels are located over the substrate and the word lines and the trench channels are alternatively arranged and each trench channel is separated from the adjacent word lines by the charge trapping structure. The bit lines are located over the word lines and each bit line is across over each of the word lines and each trench channel is electrically coupled to the bit lines.

摘要翻译： 本发明提供一种存储器阵列。 存储器阵列包括衬底，多个字线，电荷俘获结构，多个沟槽沟道和多个位线。 字线位于衬底上，字线彼此平行。 电荷捕获结构覆盖每条字线的表面。 沟槽沟槽位于衬底之上，并且字线和沟槽沟槽交替布置，并且通过电荷捕获结构将每个沟槽沟道与相邻字线分开。 位线位于字线之上，并且每个位线跨越每一个字线，并且每个沟道沟道电耦合到位线。