公开(公告)号：US10475649B2

公开(公告)日：2019-11-12

申请号：US15972223

申请日：2018-05-06

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Chen Chuang ,  Fu-Che Lee ,  Ming-Feng Kuo ,  Cheng-Yu Wang ,  Hsien-Shih Chu ,  Li-Chiang Chen

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/02 ,  H01L21/027

Abstract: A patterning method includes the following steps. A hard mask layer is formed on a substrate. Mandrels are formed on the hard mask layer. Mask patterns are formed on the mandrels. Each of the mask patterns is formed on one of the mandrels. Spacers are formed on the hard mask layer. Each of the spacers is formed on a sidewall of one of the mandrels and on a sidewall of one of the mask patterns. A cover layer covering the hard mask layer, the spacers and the mask patterns is formed. A planarization process is performed to remove the cover layer on the mask patterns and the spacer and remove the mask patterns. A part of the cover layer remains between the spacers after the planarization process. The mandrels and the cover layer are removed after the planarization process.

公开(公告)号：US10249629B1

公开(公告)日：2019-04-02

申请号：US15876220

申请日：2018-01-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Chiang Chen ,  Fu-Che Lee ,  Ming-Feng Kuo ,  Chieh-Te Chen ,  Hsien-Shih Chu

IPC: H01L27/108 ,  H01L21/311 ,  H01L29/06 ,  H01L29/423 ,  H01L21/306 ,  H01L21/308 ,  H01L21/027 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/3213

Abstract: The present invention provides a method for forming buried word lines. Firstly, a substrate is provided, having a plurality of shallow trench isolations disposed therein, next, a plurality of first patterned material layers are formed on the substrate, a plurality of first recesses are disposed between every two adjacent first patterned material layers, a second patterned material layer is formed in the first recesses, and using the first patterned material layers and the second patterned material layer as the protect layers, and a first etching process is then performed, to form a plurality of second recesses in the substrate.

公开(公告)号：US10192777B2

公开(公告)日：2019-01-29

申请号：US15854765

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hsien-Shih Chu ,  Ming-Feng Kuo ,  Yi-Wang Zhan ,  Li-Chiang Chen ,  Fu-Che Lee ,  Feng-Yi Chang

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/02

Abstract: A method of fabricating an STI trench includes providing a substrate. Later, a first mask is formed to cover the substrate. The first mask includes numerous sub-masks. A first trench is disposed between each sub-mask. Subsequently, a protective layer is formed to fill up the first trench. Then, a second mask is formed to cover the first mask. The second mask includes an opening. The sub-mask directly disposed under the opening is defined as a joint STI pattern. After that, the joint STI pattern is removed to transform the first mask into a third mask. Later, the second mask is removed followed by removing the protective layer. Finally, part of the substrate is removed by taking the third mask as a mask to form numerous STI trenches.

公开(公告)号：US10141223B2

公开(公告)日：2018-11-27

申请号：US15869107

申请日：2018-01-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Chiang Chen ,  Fu-Che Lee ,  Ming-Feng Kuo

IPC: H01L21/768 ,  H01L21/321 ,  H01L21/3213 ,  H01L27/108 ,  H01L21/285 ,  H01L21/3105

Abstract: A method of improving micro-loading effect when recess etching a tungsten layer. A substrate having trenches thereon is provided. A tungsten layer is deposited on the substrate and in the trenches. A planarization process is performed to form a planarization layer on the tungsten layer. A first etching process is performed to etch the planarization layer and the tungsten layer with an etch selectivity of planarization layer:tungsten layer=1:1 until the planarization layer is completely removed. A second etching process is performed to etch the remainder of the tungsten layer to recess the tungsten layer within the trenches.

公开(公告)号：US20180294188A1

公开(公告)日：2018-10-11

申请号：US15869107

申请日：2018-01-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Chiang Chen ,  Fu-Che Lee ,  Ming-Feng Kuo

IPC: H01L21/768 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/3105 ,  H01L27/108 ,  H01L21/285

CPC classification number: H01L21/76877 ,  H01L21/28568 ,  H01L21/31058 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/76843 ,  H01L27/10891

Abstract: A method of improving micro-loading effect when recess etching a tungsten layer. A substrate having trenches thereon is provided. A tungsten layer is deposited on the substrate and in the trenches. A planarization process is performed to form a planarization layer on the tungsten layer. A first etching process is performed to etch the planarization layer and the tungsten layer with an etch selectivity of planarization layer:tungsten layer=1:1 until the planarization layer is completely removed. A second etching process is performed to etch the remainder of the tungsten layer to recess the tungsten layer within the trenches.

公开(公告)号：US10032631B1

公开(公告)日：2018-07-24

申请号：US15591132

申请日：2017-05-10

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Chiang Chen ,  Fu-Che Lee ,  Ming-Feng Kuo ,  Hsien-Shih Chu ,  Cheng-Yu Wang ,  Yu-Chen Chuang

IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  B23P15/00 ,  C03C25/00 ,  H01L21/033

Abstract: A method of fabricating a mask pattern includes providing numerous masks on a substrate. A wider trench and a narrower trench are respectively defined between the mask. Subsequently, a mask material is formed to fill in the wider trench and the narrower trench. The top surface of the mask material overlapping the wider trench is lower than the top surface of the mask material overlapping the narrower trench. A photoresist layer is formed on the mask material overlapping the wider trench. Later, the mask material overlapping the narrower trench is etched while the mask material overlapping the wider trench is protected by the photoresist layer.

公开(公告)号：US20180190538A1

公开(公告)日：2018-07-05

申请号：US15854765

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hsien-Shih Chu ,  Ming-Feng Kuo ,  Yi-Wang Zhan ,  Li-Chiang Chen ,  Fu-Che Lee ,  Feng-Yi Chang

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3065

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76229 ,  H01L29/0649

Abstract: A method of fabricating an STI trench includes providing a substrate. Later, a first mask is formed to cover the substrate. The first mask includes numerous sub-masks. A first trench is disposed between each sub-mask. Subsequently, a protective layer is formed to fill up the first trench. Then, a second mask is formed to cover the first mask. The second mask includes an opening. The sub-mask directly disposed under the opening is defined as a joint STI pattern. After that, the joint STI pattern is removed to transform the first mask into a third mask. Later, the second mask is removed followed by removing the protective layer. Finally, part of the substrate is removed by taking the third mask as a mask to form numerous STI trenches.

公开(公告)号：US09553026B1

公开(公告)日：2017-01-24

申请号：US14960447

申请日：2015-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Chien-Ting Lin ,  Li-Chiang Chen ,  Jyh-Shyang Jenq

IPC: H01L21/30 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/088 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/3086 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first mandrel, a second mandrel, a third mandrel, and a fourth mandrel are formed on the substrate. Preferably, the first mandrel and the second mandrel include a first gap therebetween, the second mandrel and the third mandrel include a second gap therebetween, and the third mandrel and the fourth mandrel include a third gap therebetween, in which the first gap is equivalent to the third gap but different from the second gap. Next, spacers are formed adjacent to the first mandrel, the second mandrel, the third mandrel, and the fourth mandrel, and the spacers in the first gap and the third gap are removed.

Abstract translation: 公开了半导体器件的制造方法。 首先，设置基板，在基板上形成第一芯轴，第二心轴，第三心轴，第四心轴。 优选地，第一心轴和第二心轴包括其间的第一间隙，第二心轴和第三心轴在其间包括第二间隙，并且第三心轴和第四心轴在其间包括第三间隙，其中第一间隙等于 第三个差距，但与第二个差距不同。 接下来，在第一心轴，第二心轴，第三心轴和第四心轴附近形成间隔物，并且去除第一间隙和第三间隙中的间隔物。

公开(公告)号：US09165997B2

公开(公告)日：2015-10-20

申请号：US14583122

申请日：2014-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shui-Yen Lu ,  Li-Chiang Chen

IPC: H01L21/20 ,  H01L21/332 ,  H01L49/02 ,  H01L27/06 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L28/20 ,  H01L21/76897 ,  H01L27/0629 ,  H01L28/24 ,  H01L29/66545

Abstract: A semiconductor structure includes a substrate, a resist layer, a dielectric material, two U-shaped metal layers and two metals. The substrate has an isolation structure. The resist layer is located on the isolation structure. The dielectric material is located on the resist layer. Two U-shaped metal layers are located at the two sides of the dielectric material and on the resist layer. Two metals are respectively located on the two U-shaped metal layers. This way a semiconductor process for forming said semiconductor structure is provided.

Abstract translation: 半导体结构包括基板，抗蚀剂层，电介质材料，两个U形金属层和两种金属。 衬底具有隔离结构。 抗蚀剂层位于隔离结构上。 介电材料位于抗蚀剂层上。 两个U形金属层位于电介质材料的两侧和抗蚀剂层上。 两个金属分别位于两个U形金属层上。 以这种方式提供了用于形成所述半导体结构的半导体工艺。