公开(公告)号：US10199228B2

公开(公告)日：2019-02-05

申请号：US15479292

申请日：2017-04-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Nien-Ting Ho ,  Chien-Hao Chen ,  Hsin-Fu Huang ,  Chi-Yuan Sun ,  Wei-Yu Chen ,  Min-Chuan Tsai ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC: H01L21/76 ,  H01L21/28 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

Abstract: A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.

公开(公告)号：US09558996B2

公开(公告)日：2017-01-31

申请号：US14480648

申请日：2014-09-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Mao Hsu ,  Hsin-Fu Huang ,  Min-Chuan Tsai ,  Chien-Hao Chen ,  Wei-Yu Chen ,  Chin-Fu Lin ,  Jing-Gang Li ,  Min-Hsien Chen ,  Jian-Hong Su

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/28 ,  H01L29/66 ,  H01L23/522 ,  H01L23/532 ,  H01L29/51

CPC classification number: H01L21/76846 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/2855 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer. The present invention further provides a semiconductor device having an aluminum layer with a reflectivity greater than 1, wherein the semiconductor device is formed by using the method.

Abstract translation: 公开了一种用金属层填充沟槽的方法。 提供具有多个支撑销的沉积装置。 设置有基板和介电层。 电介质层具有沟槽。 在将基板放置在支撑销上以在沟槽中形成金属层之后立即执行第一沉积工艺，其中在第一沉积工艺期间，基板的温度逐渐增加以达到预定温度。 当基板的温度达到预定温度时，执行第二沉积工艺以用金属层完全填充沟槽。 本发明还提供了具有大于1的反射率的铝层的半导体器件，其中通过使用该方法形成半导体器件。

公开(公告)号：US09018086B2

公开(公告)日：2015-04-28

申请号：US14105198

申请日：2013-12-13

Applicant: United Microelectronics Corp.

Inventor： Chi-Mao Hsu ,  Hsin-Fu Huang ,  Chin-Fu Lin ,  Min-Chuan Tsai ,  Wei-Yu Chen ,  Chien-Hao Chen

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L29/76 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28026 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

Abstract: The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate.

Abstract translation: 本发明提供一种形成具有金属栅极的半导体器件的方法。 提供基板，并且在其上形成栅极电介质和功函数金属层，其中功函数金属层在栅极电介质层上。 然后，在功函数金属层上形成顶部阻挡层。 形成顶部阻挡层的步骤包括增加顶部阻挡层中边界保护材料的浓度。 最后，在顶部阻挡层上形成金属层。 本发明还提供一种具有金属栅极的半导体器件。