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公开(公告)号:US20180277679A1
公开(公告)日:2018-09-27
申请号:US15985683
申请日:2018-05-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Wei-Lun Hsu , Hsin-Che Huang , Shyan-Liang Chou , Hung-Lin Shih
IPC: H01L29/78 , H01L21/8238 , H01L21/02 , H01L29/06 , H01L27/092 , H01L21/762
CPC classification number: H01L29/7846 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L27/092 , H01L27/0924 , H01L29/0649
Abstract: A method for forming a complementary metal oxide semiconductor device is disclosed. First, a substrate having a first device region and a second device region is provided. A first trench is formed in the first device region and filled with a first material. A second trench is formed in the second device region and filled with a second material. The first material and the second material comprise different stresses. After that, a first gate structure and a second gate structure are formed on the first material and the second material and completely covering the first trench and the second trench, respectively.
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公开(公告)号:US20180269107A1
公开(公告)日:2018-09-20
申请号:US15458038
申请日:2017-03-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Yat-Kai Sun , Chao-Nan Chen , Hung-Lin Shih , Che-Hung Huang , Wei-Lun Hsu , Cheng-Chia Liu
IPC: H01L21/8234 , H01L21/02 , H01L21/3115 , H01L21/311 , H01L21/3213 , H01L21/033 , H01L21/308 , H01L29/66
Abstract: A method of forming a semiconductor device includes following steps. First of all, plural mandrel patterns are formed on a target layer. Then, plural capping layers are formed to cover a top region and sidewalls of each of the mandrel patterns, respectively. Next, plural spacers are formed at two sides of each of the capping layers, respectively. Following these, a portion of the spacers and the capping layers covered on the top regions of the mandrel patterns are simultaneously removed, and the capping layers is then removed completely.
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公开(公告)号:US10079180B1
公开(公告)日:2018-09-18
申请号:US15458038
申请日:2017-03-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Yat-Kai Sun , Chao-Nan Chen , Hung-Lin Shih , Che-Hung Huang , Wei-Lun Hsu , Cheng-Chia Liu
IPC: H01L21/76 , H01L21/8234 , H01L21/02 , H01L21/3115 , H01L21/311 , H01L21/3213 , H01L21/033 , H01L21/308 , H01L29/66
Abstract: A method of forming a semiconductor device includes following steps. First of all, plural mandrel patterns are formed on a target layer. Then, plural capping layers are formed to cover a top region and sidewalls of each of the mandrel patterns, respectively. Next, plural spacers are formed at two sides of each of the capping layers, respectively. Following these, a portion of the spacers and the capping layers covered on the top regions of the mandrel patterns are simultaneously removed, and the capping layers is then removed completely.
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公开(公告)号:US20150064896A1
公开(公告)日:2015-03-05
申请号:US14013429
申请日:2013-08-29
Applicant: United Microelectronics Corp.
Inventor: Hung-Lin Shih , Chun-Yuan Wu , Chin-Fu Lin , Chih-Chien Liu
IPC: H01L21/28
CPC classification number: H01L21/02164 , H01L21/0217 , H01L21/30621 , H01L21/31116 , H01L21/31144 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/6653 , H01L29/66545 , H01L29/66628
Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF3 and H2 as etchants.
Abstract translation: 提供一种制造半导体器件的方法,包括以下步骤。 在基板上形成虚拟栅极结构,其中虚拟栅极结构包括虚拟栅极和堆叠的硬掩模,并且堆叠的硬掩模从底部至顶部包括第一硬掩模层和第二硬掩模层。 在虚拟栅极结构的侧壁上形成间隔物。 在基板上形成掩模层。 在掩模层中形成与第二硬掩模层对应的开口。 去除第二个硬掩模层。 去除掩模层。 执行干蚀刻工艺以去除第一硬掩模层,其中干蚀刻工艺使用NF 3和H 2作为蚀刻剂。
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公开(公告)号:US20150132966A1
公开(公告)日:2015-05-14
申请号:US14583813
申请日:2014-12-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hung-Lin Shih , Jei-Ming Chen , Chih-Chien Liu , Chin-Fu Lin , Kuan-Hsien Li
IPC: H01L21/8234 , H01L29/40
CPC classification number: H01L21/30604 , H01L21/823431 , H01L21/823462 , H01L29/401
Abstract: A method for forming a FinFET structure includes providing a substrate, a first region and a second region being defined on the substrate, a first fin structure and a second fin structure being disposed on the substrate within the first region and the second region respectively. A first oxide layer cover the first fin structure and the second fin structure. Next a first protective layer and a second protective layer are entirely formed on the substrate and the first oxide layer in sequence, the second protective layer within the first region is removed, and the first protective layer within the first region is then removed. Afterwards, the first oxide layer covering the first fin structure and the second protective layer within the second region are removed simultaneously, and a second oxide layer is formed to cover the first fin structure.
Abstract translation: 一种用于形成FinFET结构的方法包括提供衬底,第一区和限定在衬底上的第二区,分别在第一区和第二区内的衬底上设置第一鳍结构和第二鳍结构。 第一氧化物层覆盖第一鳍结构和第二鳍结构。 接下来,依次在基板和第一氧化物层上完全形成第一保护层和第二保护层,去除第一区域内的第二保护层,然后去除第一区域内的第一保护层。 之后,同时除去覆盖第二区域内的第一鳍结构和第二保护层的第一氧化物层,形成第二氧化物层以覆盖第一鳍结构。
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公开(公告)号:US09018087B2
公开(公告)日:2015-04-28
申请号:US14013429
申请日:2013-08-29
Applicant: United Microelectronics Corp.
Inventor: Hung-Lin Shih , Chun-Yuan Wu , Chin-Fu Lin , Chih-Chien Liu
IPC: H01L21/00 , H01L21/28 , H01L21/306 , H01L21/02
CPC classification number: H01L21/02164 , H01L21/0217 , H01L21/30621 , H01L21/31116 , H01L21/31144 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/6653 , H01L29/66545 , H01L29/66628
Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF3 and H2 as etchants.
Abstract translation: 提供一种制造半导体器件的方法,包括以下步骤。 在基板上形成虚拟栅极结构,其中虚拟栅极结构包括虚拟栅极和堆叠的硬掩模,并且堆叠的硬掩模从底部至顶部包括第一硬掩模层和第二硬掩模层。 在虚拟栅极结构的侧壁上形成间隔物。 在基板上形成掩模层。 在掩模层中形成与第二硬掩模层对应的开口。 去除第二个硬掩模层。 去除掩模层。 执行干蚀刻工艺以去除第一硬掩模层,其中干蚀刻工艺使用NF 3和H 2作为蚀刻剂。
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