公开(公告)号：US11508585B2

公开(公告)日：2022-11-22

申请号：US16902180

申请日：2020-06-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Ji Cui ,  Fu-Ming Huang ,  Ting-Kui Chang ,  Tang-Kuei Chang ,  Chun-Chieh Lin ,  Wei-Wei Liang ,  Liang-Guang Chen ,  Kei-Wei Chen ,  Hung Yen ,  Ting-Hsun Chang ,  Chi-Hsiang Shen ,  Li-Chieh Wu ,  Chi-Jen Liu

IPC分类号： H01L21/321 ,  C09G1/02 ,  B24B37/10 ,  B24B37/04

摘要： A method for CMP includes following operations. A dielectric structure is received. The dielectric structure includes a metal layer stack formed therein. The metal layer stack includes at least a first metal layer and a second metal layer, and the first metal layer and the second metal layer are exposed through a surface of the dielectric structure. A first composition is provided to remove a portion of the first metal layer from the surface of the dielectric structure. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed from the second metal layer. A CMP operation is performed to remove a portion of the second metal layer. In some embodiments, the protecting layer protects the second metal layer during the removal of the portion of the first metal layer.

公开(公告)号：US11380762B2

公开(公告)日：2022-07-05

申请号：US16601281

申请日：2019-10-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238 ,  H01L21/02

摘要： A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

公开(公告)号：US11322345B2

公开(公告)日：2022-05-03

申请号：US16390691

申请日：2019-04-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Fu-Ming Huang ,  Liang-Guang Chen ,  Ting-Kui Chang ,  Chun-Chieh Lin

IPC分类号： H01L21/02 ,  H01L21/67 ,  H01L21/687 ,  H01L21/306 ,  B08B1/00 ,  B08B1/04 ,  B08B3/04

摘要： A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.

公开(公告)号：US10916473B2

公开(公告)日：2021-02-09

申请号：US16655509

申请日：2019-10-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Hao Chung ,  Chang-Sheng Lin ,  Kuo-Feng Huang ,  Li-Chieh Wu ,  Chun-Chieh Lin

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L23/535 ,  H01L21/285 ,  H01L23/485

摘要： A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.

公开(公告)号：US10818754B2

公开(公告)日：2020-10-27

申请号：US15913414

申请日：2018-03-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

IPC分类号： H01L29/10 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

摘要： A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

公开(公告)号：US10510594B2

公开(公告)日：2019-12-17

申请号：US16050168

申请日：2018-07-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Hao Chung ,  Chang-Sheng Lin ,  Kuo-Feng Huang ,  Li-Chieh Wu ,  Chun-Chieh Lin

IPC分类号： H01L21/768 ,  H01L23/535 ,  H01L21/02 ,  H01L21/285 ,  H01L23/485

摘要： A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.

公开(公告)号：US20170256488A1

公开(公告)日：2017-09-07

申请号：US15600941

申请日：2017-05-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ya-Lien Lee ,  Chun-Chieh Lin

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5222 ,  H01L21/76813 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76879 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a first conductive line, a dielectric layer over the first conductive line, a diffusion barrier layer in the dielectric layer, and a second conductive line in the dielectric layer. The second conductive line includes a first portion of the diffusion barrier layer. A via is underlying the second conductive line and electrically couples the second conductive line to the first conductive line. The via includes a second portion of the diffusion barrier layer, with the second portion of the diffusion barrier layer having a bottom end higher than a bottom surface of the via.

公开(公告)号：US20210053180A1

公开(公告)日：2021-02-25

申请号：US16550021

申请日：2019-08-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Michael Yen ,  Kao-Feng Liao ,  Hsin-Ying Ho ,  Chun-Wen Hsiao ,  Sheng-Chao Chuang ,  Ting-Hsun Chang ,  Fu-Ming Huang ,  Chun-Chieh Lin ,  Peng-Chung Jangjian ,  Ji James Cui ,  Liang-Guang Chen ,  Chih Hung Chen ,  Kei-Wei Chen

IPC分类号： B24B37/26 ,  B24B37/24 ,  B24B37/005

摘要： A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.

公开(公告)号：US10269555B2

公开(公告)日：2019-04-23

申请号：US14870946

申请日：2015-09-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Fu-Ming Huang ,  Liang-Guang Chen ,  Ting-Kui Chang ,  Chun-Chieh Lin

IPC分类号： B08B7/00 ,  H01L21/02 ,  B08B1/00 ,  B08B1/04 ,  B08B3/04 ,  H01L21/306 ,  H01L21/67 ,  H01L21/687

摘要： A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.

公开(公告)号：US20180350675A1

公开(公告)日：2018-12-06

申请号：US16050168

申请日：2018-07-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Hao Chung ,  Chang-Sheng Lin ,  Kuo-Feng Huang ,  Li-Chieh Wu ,  Chun-Chieh Lin

IPC分类号： H01L21/768 ,  H01L23/535

CPC分类号： H01L21/76883 ,  H01L21/02074 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/535

摘要： A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.