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    Differential sensing with BioFET sensors
    11.
    发明授权
    Differential sensing with BioFET sensors 有权

    公开(公告)号：US11624726B2

    公开(公告)日：2023-04-11

    申请号：US17208596

    申请日：2021-03-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ching-Hui Lin ,  Chun-Ren Cheng ,  Shih-Fen Huang ,  Fu-Chun Huang

    IPC: G01N27/414 ,  G01N27/30 ,  B01L3/00

    Abstract: A sensor array includes a semiconductor substrate, a first plurality of FET sensors and a second plurality of FET sensors. Each of the FET sensors includes a channel region between a source and a drain region in the semiconductor substrate and underlying a gate structure disposed on a first side of the channel region, and a dielectric layer disposed on a second side of the channel region opposite from the first side of the channel region. A first plurality of capture reagents is coupled to the dielectric layer over the channel region of the first plurality of FET sensors, and a second plurality of capture reagents is coupled to the dielectric layer over the channel region of the second plurality of FET sensors. The second plurality of capture reagents is different from the first plurality of capture reagents.

    Plate design to decrease noise in semiconductor devices
    12.
    发明授权
    Plate design to decrease noise in semiconductor devices 有权

    公开(公告)号：US11011610B2

    公开(公告)日：2021-05-18

    申请号：US16837444

    申请日：2020-04-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

    IPC: H01L29/78 ,  H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49

    Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

    FATIGUE-FREE BIPOLAR LOOP TREATMENT TO REDUCE IMPRINT EFFECT IN PIEZOELECTRIC DEVICE
    13.
    发明申请
    FATIGUE-FREE BIPOLAR LOOP TREATMENT TO REDUCE IMPRINT EFFECT IN PIEZOELECTRIC DEVICE 有权

    公开(公告)号：US20210043680A1

    公开(公告)日：2021-02-11

    申请号：US16534330

    申请日：2019-08-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Yuan Shih ,  Shih-Fen Huang ,  You-Ru Lin ,  Yan-Jie Liao

    IPC: H01L27/20 ,  H01L41/09 ,  H01L41/314

    Abstract: In some embodiments, the present disclosure relates to a method for recovering degraded device performance of a piezoelectric device. The method includes operating the piezoelectric device in a performance mode by applying one or more voltage pulses to the piezoelectric device, and determining that a performance parameter of the piezoelectric device has a first value that has deviated from a reference value by more than a predetermined threshold value during a first time period. During a second time period, the method further includes applying a bipolar loop to the piezoelectric device, comprising positive and negative voltage biases. During a third time period, the method further includes operating the piezoelectric device in the performance mode, wherein the performance parameter has a second value. An absolute difference between the second value and the reference value is less than an absolute difference between the first value and the reference value.

    PLATE DESIGN TO DECREASE NOISE IN SEMICONDUCTOR DEVICES
    14.
    发明申请
    PLATE DESIGN TO DECREASE NOISE IN SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20200227529A1

    公开(公告)日：2020-07-16

    申请号：US16837444

    申请日：2020-04-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

    IPC: H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08

    Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

    Plate design to decrease noise in semiconductor devices
    15.
    发明授权
    Plate design to decrease noise in semiconductor devices 有权

    公开(公告)号：US10658482B2

    公开(公告)日：2020-05-19

    申请号：US15800474

    申请日：2017-11-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

    IPC: H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49

    Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

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