公开(公告)号：US11489056B2

公开(公告)日：2022-11-01

申请号：US16785919

申请日：2020-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Peng-Soon Lim ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L27/092 ,  B82Y10/00

Abstract: The present disclosure describes a semiconductor device that includes a substrate and a first transistor on the substrate. The first transistor includes a first gate structure and the first gate structure includes a gate dielectric layer and a first work function layer on the gate dielectric layer. The first gate structure also includes a capping layer on the first work function layer. The semiconductor device also includes a second transistor on the substrate, in which the second transistor includes a second gate structure. The second gate structure includes the gate dielectric layer and a second work function layer on the gate dielectric layer. The second gate structure also includes the first work function layer on the second work function layer and the silicon capping layer on the first work function layer.

公开(公告)号：US20220278224A1

公开(公告)日：2022-09-01

申请号：US17663979

申请日：2022-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peng-Soon Lim ,  Cheng-Lung Hung ,  Mao-Lin Huang ,  Weng Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49

Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

公开(公告)号：US11282933B2

公开(公告)日：2022-03-22

申请号：US16031859

申请日：2018-07-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Peng-Soon Lim ,  Zi-Wei Fang ,  Cheng-Ming Lin

IPC: H01L29/78 ,  H01L29/423 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L21/28 ,  H01L29/10 ,  H01L29/417

Abstract: A semiconductor device includes a semiconductor substrate having a channel region. A gate dielectric layer is over the channel region of the semiconductor substrate. A work function metal layer is over the gate dielectric layer. The work function metal layer has a bottom portion, an upper portion, and a work function material. The bottom portion is between the gate dielectric layer and the upper portion. The bottom portion has a first concentration of the work function material, the upper portion has a second concentration of the work function material, and the first concentration is higher than the second concentration. A gate electrode is over the upper portion of the work function metal layer.

公开(公告)号：US11984356B2

公开(公告)日：2024-05-14

申请号：US17519242

申请日：2021-11-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peng-Soon Lim ,  Chung-Liang Cheng ,  Huang-Lin Chao

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088

CPC classification number: H01L21/76871 ,  H01L21/76804 ,  H01L21/76865 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/088 ,  H01L21/76843 ,  H01L21/823412 ,  H01L21/823456

Abstract: A semiconductor device with liner-free contact structures and a method of fabricating the same are disclosed. The method includes forming first and second source/drain (S/D) regions on first and second fin structures, forming a first dielectric layer between the first and second S/D regions, forming first and second gate-all-around (GAA) structures on the first and second fin structures, forming a second dielectric layer on the first and second GAA structures and the first dielectric layer, forming a tapered trench opening in the second dielectric layer and on the first and second GAA structures and the first dielectric layer, selectively forming a seed layer on top surfaces of the first and second GAA structures and the first dielectric layer that are exposed in the tapered trench opening, and selectively depositing a conductive layer on the seed layer to fill the tapered trench opening.

公开(公告)号：US11018232B2

公开(公告)日：2021-05-25

申请号：US16875877

申请日：2020-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming Lin ,  Peng-Soon Lim ,  Zi-Wei Fang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate, a pair of source/drain regions, and a gate stack. The pair of source/drain regions is on the semiconductor substrate. The gate stack is laterally between the source/drain regions and includes a gate dielectric layer over the semiconductor fin, a metal element-containing layer over the gate dielectric layer, and a fill metal layer over the metal element-containing layer. The metal element-containing layer has a dopant, and a concentration of the dopant in an upper portion of the metal element-containing layer is higher than a concentration of the dopant in a bottom portion of the metal element-containing layer.

公开(公告)号：US10707131B2

公开(公告)日：2020-07-07

申请号：US16103724

申请日：2018-08-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Peng-Soon Lim ,  Zi-Wei Fang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/285 ,  H01L29/66

Abstract: A method includes forming in sequence a metallic capping layer and a dummy gate electrode layer over a semiconductor substrate; patterning the metallic capping layer and the dummy gate electrode layer to form a first stacked structure including a first portion of the metallic capping layer and a first portion of the dummy gate electrode layer; forming a plurality of first gate spacers on opposite sides of the first stacked structure; removing the first portion of the dummy gate electrode layer to expose the first portion of the metallic capping layer; and forming a first work function metal layer on the first portion of the metallic capping layer.