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公开(公告)号：US09991333B1
公开(公告)日：2018-06-05
申请号：US15428678
申请日：2017-02-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ming-Chyi Liu , Shih-Chang Liu
IPC: H01L27/108 , H01L29/94 , H01L49/02
Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the MIM capacitor are provided. The MIM capacitor structure includes a substrate. A MIM capacitor is formed on the substrate. The MIM capacitor includes a U-shaped electrode having a first portion. The MIM capacitor also includes an inverted U-shaped electrode. The first portion of the U-shaped electrode is clamped by the inverted U-shaped electrode. The MIM capacitor further includes an insulating film between the U-shaped electrode and the inverted U-shaped electrode.
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公开(公告)号：US09935139B2
公开(公告)日：2018-04-03
申请号：US14466308
申请日：2014-08-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
Inventor： Ming-Chyi Liu
IPC: H01L27/146
CPC classification number: H01L27/14612 , H01L27/14614 , H01L27/1463 , H01L27/14643 , H01L27/14689
Abstract: An image sensor and a method for forming an image sensor are provided. The image sensor includes a substrate, and the substrate includes a pixel region, a peripheral region and a boundary region, and the boundary region is formed between the pixel region and the peripheral region. The image sensor also includes a first gate stack structure formed in the pixel region and a second gate stack structure formed in the peripheral region. The second gate stack structure includes a high-k dielectric layer and a first metal layer.
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公开(公告)号：US20170345835A1
公开(公告)日：2017-11-30
申请号：US15216872
申请日：2016-07-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ming-Chyi Liu , Shih-Chang Liu , Sheng-Chieh Chen
IPC: H01L27/11526 , H01L27/11521 , H01L27/11519 , H01L27/11556 , H01L27/105
CPC classification number: H01L27/11526 , H01L27/1052 , H01L27/11519 , H01L27/11521 , H01L27/11556 , H01L29/42328
Abstract: The present disclosure relates to an improved integrated circuit having an embedded flash memory device with a word line having its height reduced, and associated processing methods. In some embodiments, the flash memory device includes a gate stack separated from a substrate by a gate dielectric. The gate stack includes a control gate separated from a floating gate by a control gate dielectric. An erase gate is disposed on a first side of the gate stack and a word line is disposed on a second side of the gate stack that is opposite to the first side. The word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack. A word line height at the outer side is smaller than an erase gate height.
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公开(公告)号：US09219109B2
公开(公告)日：2015-12-22
申请号：US14712329
申请日：2015-05-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
Inventor： Yuan-Tai Tseng , Ming-Chyi Liu , Chung-Yen Chou , Chia-Shiung Tsai
CPC classification number: H01F27/2804 , H01F1/0306 , H01F17/0013 , H01F17/0033 , H01F27/24 , H01F2017/0066 , H01F2027/2809 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
Abstract: The mechanisms for forming an inductor structure are provided. The inductor structure includes a substrate and a first dielectric layer formed over the substrate. The inductor structure also includes a first metal layer formed in the first dielectric layer and a magnetic layer formed over the first dielectric layer, and the magnetic layer has edges more than four in a cross section view.
Abstract translation: 提供了形成电感器结构的机构。 电感器结构包括衬底和形成在衬底上的第一介电层。 电感器结构还包括形成在第一电介质层中的第一金属层和形成在第一介电层上的磁性层，并且磁性层在截面图中具有超过四个的边缘。
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公开(公告)号：US11742262B2
公开(公告)日：2023-08-29
申请号：US17233676
申请日：2021-04-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yuan-Tai Tseng , Chia-Shiung Tsai , Chung-Yen Chou , Ming-Chyi Liu
IPC: H01L23/485 , H01C17/075 , H01C7/00 , H01L23/522 , H01L23/532 , H01L21/70 , H01L21/768 , H01L49/02
CPC classification number: H01L23/485 , H01C7/006 , H01C17/075 , H01L21/707 , H01L21/7685 , H01L21/76846 , H01L21/76849 , H01L21/76895 , H01L23/5228 , H01L28/24 , H01L23/5329 , H01L23/53238 , H01L2924/0002 , H01L2924/0002 , H01L2924/00
Abstract: A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.
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Patent Agency Ranking
公开(公告)号：US11545584B2
公开(公告)日：2023-01-03
申请号：US17230906
申请日：2021-04-14
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yong-Sheng Huang , Ming-Chyi Liu
IPC: H01L29/792 , H01L29/06 , H01L29/423 , H01L29/66 , H01L21/28 , H01L21/762
Abstract: A memory device includes an active region, a select gate, a control gate, and a blocking layer. The active region includes a bottom portion and a protruding portion protruding from the bottom portion. A source is in the bottom portion and a drain is in the protruding portion. The select gate is above the bottom portion. A top surface of the select gate is lower than a top surface of the protruding portion. The control gate is above the bottom portion. The blocking layer is between the select gate and the control gate.
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公开(公告)号：US20210242109A1
公开(公告)日：2021-08-05
申请号：US17233676
申请日：2021-04-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yuan-Tai Tseng , Chia-Shiung Tsai , Chung-Yen Chou , Ming-Chyi Liu
IPC: H01L23/485 , H01L49/02 , H01C17/075 , H01C7/00 , H01L23/522 , H01L21/70 , H01L21/768
Abstract: A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.
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公开(公告)号：US20180137966A1
公开(公告)日：2018-05-17
申请号：US15853541
申请日：2017-12-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
Inventor： Yuan-Tai Tseng , Ming-Chyi Liu , Chung-Yen Chou , Chia-Shiung Tsai
CPC classification number: H01F27/2804 , H01F1/0306 , H01F17/0013 , H01F17/0033 , H01F27/24 , H01F2017/0066 , H01F2027/2809 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
Abstract: An inductor structure is provided. The inductor structure includes a first dielectric layer formed over a substrate and a magnetic layer formed over the first dielectric layer. The magnetic layer has a planar top surface, a planar bottom surface, a protruding portion surrounding the planar top surface, and the protruding portion is higher than the planar top surface.
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公开(公告)号：US09865389B2
公开(公告)日：2018-01-09
申请号：US15429272
申请日：2017-02-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
Inventor： Yuan-Tai Tseng , Ming-Chyi Liu , Chung-Yen Chou , Chia-Shiung Tsai
CPC classification number: H01F27/2804 , H01F1/0306 , H01F17/0013 , H01F17/0033 , H01F27/24 , H01F2017/0066 , H01F2027/2809 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
Abstract: An inductor structure is provided. The inductor structure includes a first dielectric layer formed over a substrate and a first metal layer formed in the first dielectric layer. The inductor structure includes a magnetic layer formed over the first dielectric layer, and the magnetic layer has a main portion and a tapered portion extending from the main portion.
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公开(公告)号：US09570536B2
公开(公告)日：2017-02-14
申请号：US14948000
申请日：2015-11-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
Inventor： Yuan-Tai Tseng , Ming-Chyi Liu , Chung-Yen Chou , Chia-Shiung Tsai
IPC: H01L29/82 , H01L49/02 , H01L23/522 , H01F17/00
CPC classification number: H01F27/2804 , H01F1/0306 , H01F17/0013 , H01F17/0033 , H01F27/24 , H01F2017/0066 , H01F2027/2809 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
Abstract: The methods for forming an inductor structure are provided. The method includes forming an oxide layer over a substrate, and the layer includes an opening. The method includes forming a magnetic material over the oxide layer and in the opening and forming a patterned photoresist layer over the magnetic material, wherein the patterned photoresist layer overlaps the opening. The method further includes performing an etching process on the magnetic material using the patterned photoresist as a mask.
Abstract translation: 提供了形成电感器结构的方法。 该方法包括在衬底上形成氧化物层，并且该层包括开口。 该方法包括在氧化物层和开口中形成磁性材料，并在磁性材料上形成图案化的光致抗蚀剂层，其中图案化的光刻胶层与开口重叠。 该方法还包括使用图案化的光致抗蚀剂作为掩模对磁性材料进行蚀刻处理。
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