公开(公告)号：US20210294130A1

公开(公告)日：2021-09-23

申请号：US16821160

申请日：2020-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Lin ,  Ming Chyi Liu

IPC: G02F1/025

Abstract: In some embodiments, the present disclosure relates to a modulator device that includes an input terminal configured to receive impingent light. A first waveguide has a first output region and a first input region that is coupled to the input terminal. A second waveguide is optically coupled to the first waveguide and has second input region and a second output region that is coupled to the input terminal. An output terminal coupled to the first output region of the first waveguide and the second output region of the second waveguide is configured to provide outgoing light that is modulated. A heater structure is configured to provide heat to the first waveguide to induce a temperature difference between the first and second waveguides. A gas-filled isolation structure is proximate to the heater structure and is configured to thermally isolate the second waveguide from the heat provided to the first waveguide.

公开(公告)号：US20210265344A1

公开(公告)日：2021-08-26

申请号：US16797334

申请日：2020-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Alexander Kalnitsky ,  Kong-Beng Thei ,  Ming Chyi Liu ,  Shi-Chung Hsiao ,  Jhih-Bin Chen

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/51 ,  H01L29/06

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

公开(公告)号：US20210132462A1

公开(公告)日：2021-05-06

申请号：US16733488

申请日：2020-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Lin ,  Ming Chyi Liu

IPC: G02F1/225

Abstract: Various embodiments of the present disclosure are directed towards a modulator device including a first waveguide and a heater structure. An input terminal is configured to receive impingent light. The first waveguide has a first output region and a first input region coupled to the input terminal. A second waveguide is optically coupled to the first waveguide. The second waveguide has a second output region and a second input region coupled to the input terminal. An output terminal is configured to provide outgoing light that is modulated based on the impingent light. The output terminal is coupled to the first output region and the second output region. The heater structure overlies the first waveguide. A bottom surface of the heater structure is aligned with a bottom surface of the first waveguide. The first waveguide is spaced laterally between sidewalls of the heater structure.

公开(公告)号：US20210111366A1

公开(公告)日：2021-04-15

申请号：US16601712

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chang Chang ,  Ming Chyi Liu

IPC: H01L51/52 ,  H01L27/32 ,  H01L51/56

Abstract: In some embodiments, the present disclosure relates to a display device that includes an isolation structure disposed over a reflector electrode, a transparent electrode disposed over the isolation structure, an optical emitter structure disposed over the transparent electrode, and a via structure. The via structure extends from the transparent electrode at a top surface of the isolation structure to a top surface of the reflector electrode. The via structure includes a center horizontal segment that contacts the top surface of the reflector electrode, a sidewall vertical segment that contacts an inner sidewall of the isolation structure, and an upper horizontal segment that is connected to the center horizontal segment by the sidewall vertical segment. The upper horizontal segment is thicker than the center horizontal segment.

公开(公告)号：US20210066323A1

公开(公告)日：2021-03-04

申请号：US16800167

申请日：2020-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yong-Sheng Huang ,  Ming Chyi Liu ,  Chih-Pin Huang

IPC: H01L27/11521 ,  H01L23/528 ,  H01L23/522 ,  H01L29/788 ,  H01L21/768 ,  H01L21/311 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

公开(公告)号：US20200075614A1

公开(公告)日：2020-03-05

申请号：US16245394

申请日：2019-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Shu Huang ,  Ming Chyi Liu

IPC: H01L27/11556 ,  H01L29/423 ,  H01L29/66 ,  G11C16/04 ,  H01L27/1158

Abstract: In some embodiments, the present disclosure relates to a flash memory structure. The flash memory structure has a source region and a drain region disposed within a substrate. A select gate is disposed over the substrate between the source region and the drain region, and a floating gate is disposed over the substrate between the select gate and the source region. A control gate is disposed over the floating gate. The floating gate has sidewalls that define protrusions extending downward from a lower surface of the floating gate to define a recess within a bottom of the floating gate.

公开(公告)号：US20190035955A1

公开(公告)日：2019-01-31

申请号：US16145585

申请日：2018-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Lee-Chuan Tseng ,  Ming Chyi Liu ,  Po-Chun Liu

IPC: H01L31/0352 ,  H01L31/103 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/02 ,  H01L31/105 ,  H01L31/18

Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. A dielectric layer is arranged over an upper surface of the silicon substrate, and extends over outer edges of the well region and includes an opening that leaves an inner portion of the well region exposed. An epitaxial pillar of SiGe or Ge extends upward from the inner portion of the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric sidewall structure surrounds the epitaxial pillar and has a bottom surface that rests on an upper surface of the dielectric layer.

公开(公告)号：US10147829B2

公开(公告)日：2018-12-04

申请号：US15273880

申请日：2016-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Lee-Chuan Tseng ,  Ming Chyi Liu ,  Po-Chun Liu

IPC: H01L31/02 ,  H01L31/05 ,  H01L31/18 ,  H01L31/028 ,  H01L31/103 ,  H01L31/0216 ,  H01L31/0312 ,  H01L31/0352 ,  H01L31/105

Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. A dielectric layer is arranged over an upper surface of the silicon substrate, and extends over outer edges of the well region and includes an opening that leaves an inner portion of the well region exposed. An epitaxial pillar of SiGe or Ge extends upward from the inner portion of the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric sidewall structure surrounds the epitaxial pillar and has a bottom surface that rests on an upper surface of the dielectric layer.

公开(公告)号：US09425044B2

公开(公告)日：2016-08-23

申请号：US14461565

申请日：2014-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/788 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L21/02601 ,  H01L21/02532 ,  H01L21/28273 ,  H01L21/3213 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7881

Abstract: Some embodiments relate to a memory device comprising a charge-trapping layer disposed between a control gate and a select gate. A capping structure is disposed over an upper surface of the control gate, and a composite spacer is disposed on a source-facing sidewall surface of the control gate. The capping structure and the composite spacer prevent damage to the control gate during one more etch processes used for contact formation to the memory device. To further limit or prevent the select gate sidewall etching, some embodiments provide for an additional liner oxide layer disposed along the drain-facing sidewall surface of the select gate. The liner oxide layer is configured as an etch stop layer to prevent etching of the select gate during the one or more etch processes. As a result, the one or more etch processes leave the control gate and select gate substantially intact.

Abstract translation: 一些实施例涉及包括设置在控制栅极和选择栅极之间的电荷捕获层的存储器件。 封盖结构设置在控制栅极的上表面上，并且复合间隔物设置在控制栅极的面向源的侧壁表面上。 封盖结构和复合间隔物在用于与存储器件的接触形成的一个以上蚀刻工艺期间防止对控制栅极的损坏。 为了进一步限制或防止选择栅极侧壁蚀刻，一些实施例提供沿着选择栅极的面向排水的侧壁表面设置的附加衬垫氧化物层。 衬里氧化物层被配置为蚀刻停止层，以防止在一个或多个蚀刻工艺期间蚀刻选择栅极。 结果，一个或多个蚀刻工艺离开控制栅极并基本上完整地选择栅极。

公开(公告)号：US09224615B2

公开(公告)日：2015-12-29

申请号：US14023563

申请日：2013-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Ming Chang ,  Lee-Chuan Tseng ,  Shih-Wei Lin ,  Chih-Jen Chan ,  Yuan-Chih Hsieh ,  Ming Chyi Liu ,  Chung-Yen Chou

IPC: H01L21/265 ,  H01L21/3065 ,  H01L27/00 ,  H01L21/263

CPC classification number: H01L21/30655 ,  H01L21/2633 ,  H01L21/3065 ,  H01L27/00

Abstract: A method of etching a trench in a substrate is provided. The method repeatedly alternates between using a fluorine-based plasma to etch a trench, which has trench sidewalls, into a selected region of the substrate; and using a fluorocarbon plasma to deposit a liner on the trench sidewalls. The liner, when formed and subsequently etched, has an exposed sidewall surface that includes scalloped recesses. The trench, which includes the scalloped recesses, is then bombarded with a molecular beam where the molecules are directed on an axis parallel to the trench sidewalls to reduce the scalloped recesses.

Abstract translation: 提供了蚀刻衬底中的沟槽的方法。 该方法在使用氟基等离子体之间重复地交替，以将具有沟槽侧壁的沟槽蚀刻到衬底的选定区域中; 以及使用氟碳等离子体将衬垫沉积在沟槽侧壁上。 衬里当形成并随后被蚀刻时具有包括扇形凹槽的暴露的侧壁表面。 包括扇形凹槽的沟槽然后用分子束轰击，其中分子被引导在平行于沟槽侧壁的轴上以减少扇形凹部。