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公开(公告)号：US20210384349A1
公开(公告)日：2021-12-09
申请号：US17408846
申请日：2021-08-23
发明人： Po-Yu Chen , Wan-Hua Huang , Jing-Ying Chen , Kuo-Ming Wu
摘要： A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.
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公开(公告)号：US11145713B2
公开(公告)日：2021-10-12
申请号：US16601998
申请日：2019-10-15
发明人： Karthick Murukesan , Wen-Chih Chiang , Chun Lin Tsai , Ker-Hsiao Huo , Kuo-Ming Wu , Po-Chih Chen , Ru-Yi Su , Shiuan-Jeng Lin , Yi-Min Chen , Hung-Chou Lin , Yi-Cheng Chiu
IPC分类号： H01L29/06 , H01L29/66 , H01L29/78 , H01L21/8234 , H01L29/10 , H03K19/0185 , H01L27/088 , H01L27/092 , H01L21/8238 , H01L29/08 , H01L29/423 , H01L29/40
摘要： Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.
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公开(公告)号：US20210159334A1
公开(公告)日：2021-05-27
申请号：US17142618
申请日：2021-01-06
发明人： Hung-Chou Lin , Yi-Cheng Chiu , Karthick Murukesan , Yi-Min Chen , Shiuan-Jeng Lin , Wen-Chih Chiang , Chen-Chien Chang , Chih-Yuan Chan , Kuo-Ming Wu , Chun Lin Tsai
IPC分类号： H01L29/78 , H01L29/08 , H01L29/40 , H01L29/06 , H01L29/423
摘要： A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
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公开(公告)号：US20210134663A1
公开(公告)日：2021-05-06
申请号：US17038198
申请日：2020-09-30
IPC分类号： H01L21/768 , H01L25/00 , H01L23/528 , H01L25/065 , H01L23/48 , H01L23/522 , H01L23/00
摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
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公开(公告)号：US10734285B2
公开(公告)日：2020-08-04
申请号：US16178819
申请日：2018-11-02
IPC分类号： H01L21/822 , H01L23/532 , H01L23/528 , H01L23/522 , H01L21/768 , H01L23/00 , H01L25/065
摘要： In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.
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16.发明申请公开(公告)号：US20200044014A1
公开(公告)日：2020-02-06
申请号：US16601998
申请日：2019-10-15
发明人： Karthick Murukesan , Wen-Chih Chiang , Chun Lin Tsai , Ker-Hsiao Huo , Kuo-Ming Wu , Po-Chih Chen , Ru-Yi Su , Shiuan-Jeng Lin , Yi-Min Chen , Hung-Chou Lin , Yi-Cheng Chiu
IPC分类号： H01L29/06 , H01L29/66 , H01L29/78 , H01L21/8234 , H01L29/10 , H03K19/0185 , H01L27/088
摘要： Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.
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公开(公告)号：US20190109125A1
公开(公告)日：2019-04-11
申请号：US16201113
申请日：2018-11-27
发明人： Kuo-Ming Wu , Kuan-Liang Liu , Wen-De Wang , Yung-Lung Lin
摘要： Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.
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18.发明申请公开(公告)号：US20190096988A1
公开(公告)日：2019-03-28
申请号：US15964636
申请日：2018-04-27
发明人： Karthick Murukesan , Wen-Chih Chiang , Chun Lin Tsai , Ker-Hsiao Huo , Kuo-Ming Wu , Po-Chih Chen , Ru-Yi Su , Shiuan-Jeng Lin , Yi-Min Chen , Hung-Chou Lin , Yi-Cheng Chiu
摘要： Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.
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公开(公告)号：US11984431B2
公开(公告)日：2024-05-14
申请号：US18156848
申请日：2023-01-19
发明人： Kuo-Ming Wu , Yung-Lung Lin , Zhi-Yang Wang , Sheng-Chau Chen , Cheng-Hsien Chou
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00
CPC分类号： H01L25/0657 , H01L24/02 , H01L24/06 , H01L25/50
摘要： A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.
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公开(公告)号：US11935950B2
公开(公告)日：2024-03-19
申请号：US17408846
申请日：2021-08-23
发明人： Po-Yu Chen , Wan-Hua Huang , Jing-Ying Chen , Kuo-Ming Wu
CPC分类号： H01L29/7835 , H01L29/66659 , H01L29/66681 , H01L29/0653 , H01L29/1087 , H01L29/456 , H01L29/4933 , H01L29/665
摘要： A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.
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