公开(公告)号：US20200251571A1

公开(公告)日：2020-08-06

申请号：US16690005

申请日：2019-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung TSAI ,  Clement Hsingjen WANN ,  Kuo-Feng YU ,  Ming-Hsi YEH ,  Shahaji B. MORE ,  Yu-Ming LIN

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8234

Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.

公开(公告)号：US20190363176A1

公开(公告)日：2019-11-28

申请号：US16517204

申请日：2019-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. MORE ,  Chun-Hsiung TSAI ,  Cheng-Yi PENG ,  Shih-Chieh CHANG ,  Kuo-Feng YU

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: Methods for forming semiconductor structures are provided. The method includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method further includes recessing the fin structure to form a recess and implanting dopants from the recess to form a doped region. The method further includes diffusing the dopants in the doped region to form an expanded doped region and forming a source/drain structure over the expanded doped region.

公开(公告)号：US20190097051A1

公开(公告)日：2019-03-28

申请号：US15893081

申请日：2018-02-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung TSAI ,  Shahaji B. MORE ,  Cheng-Yi PENG ,  Yu-Ming LIN ,  Kuo-Feng YU ,  Ziwei FANG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/45 ,  H01L29/165 ,  H01L27/088 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/06

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure extended above a substrate and a gate structure formed over a middle portion of the fin structure. The middle portion of the fin structure is wrapped by the gate structure. The FinFET device structure includes a source/drain (S/D) structure adjacent to the gate structure, and the S/D structure includes a doped region at an outer portion of the S/D structure, and the doped region includes gallium (Ga). The FinFET device structure includes a metal silicide layer formed over the doped region of the S/D structure, and the metal silicide layer is in direct contact with the doped region of the S/D structure.

公开(公告)号：US20160315191A1

公开(公告)日：2016-10-27

申请号：US14853839

申请日：2015-09-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung TSAI ,  Kuo-Feng YU ,  Kei-Wei CHEN

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/225 ,  H01L21/223 ,  H01L21/324 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7834 ,  H01L21/2236 ,  H01L21/2254 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66492 ,  H01L29/66803

Abstract: A semiconductor structure includes a substrate, a first semiconductor fin, a second semiconductor fin, and a first lightly-doped drain (LDD) region. The first semiconductor fin is disposed on the substrate. The first semiconductor fin has a top surface and sidewalls. The second semiconductor fin is disposed on the substrate. The first semiconductor fin and the second semiconductor fin are separated from each other at a nanoscale distance. The first lightly-doped drain (LDD) region is disposed at least in the top surface and the sidewalls of the first semiconductor fin.

Abstract translation: 半导体结构包括衬底，第一半导体鳍片，第二半导体鳍片和第一轻掺杂漏极（LDD）区域。 第一半导体鳍片设置在基板上。 第一半导体鳍具有顶表面和侧壁。 第二半导体翅片设置在基板上。 第一半导体鳍片和第二半导体鳍片以纳米级距离彼此分离。 第一轻掺杂漏极（LDD）区域至少设置在第一半导体鳍片的顶表面和侧壁中。