公开(公告)号：US10854723B2

公开(公告)日：2020-12-01

申请号：US15665276

申请日：2017-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hao Wang ,  Wai-Yi Lien ,  Shi-Ning Ju ,  Kai-Chieh Yang ,  Wen-Ting Lan

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/06

Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure.

公开(公告)号：US12272600B2

公开(公告)日：2025-04-08

申请号：US17663302

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Wen Chen ,  Chang-Ting Chung ,  Yi-Hsiang Chao ,  Yu-Ting Wen ,  Kai-Chieh Yang ,  Yu-Chen Ko ,  Peng-Hao Hsu ,  Ya-Yi Cheng ,  Min-Hsiu Hung ,  Chun-Hsien Huang ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/535

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

公开(公告)号：US12211921B2

公开(公告)日：2025-01-28

申请号：US17576854

申请日：2022-01-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Kai-Chieh Yang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: Aspects of the disclosure provide a method for forming a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.

公开(公告)号：US20240379849A1

公开(公告)日：2024-11-14

申请号：US18783087

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chieh Yang ,  Wei Ju Lee ,  Li-Yang Chuang ,  Pei-Yu Wang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

公开(公告)号：US12062705B2

公开(公告)日：2024-08-13

申请号：US17106933

申请日：2020-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hao Wang ,  Shi-Ning Ju ,  Kai-Chieh Yang ,  Wen-Ting Lan ,  Wai-Yi Lien

IPC: H01L29/423 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/823487 ,  H01L21/823885 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/0649

Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure.

公开(公告)号：US11923457B2

公开(公告)日：2024-03-05

申请号：US17850251

申请日：2022-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Yu Yang ,  Kai-Chieh Yang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/08 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/31116 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate, wherein the semiconductor fin includes a channel region and a source/drain region; a gate structure disposed over the channel region of the semiconductor fin, wherein the gate structure includes a gate spacer and a gate stack; a source/drain structure disposed over the source/drain region of the semiconductor fin; and a fin top hard mask vertically interposed between the gate spacer and the semiconductor fin, wherein the fin top hard mask includes a dielectric layer, and wherein a sidewall of the fin top hard mask directly contacts the gate stack, and another sidewall of the fin top hard mask directly contacts the source/drain structure.

公开(公告)号：US20210313235A1

公开(公告)日：2021-10-07

申请号：US17340660

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Kai-Chieh Yang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3065 ,  H01L27/092

Abstract: In an embodiment, a method includes: forming a first recess and a second recess in a substrate; growing a first epitaxial material stack in the first recess, the first epitaxial material stack including alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; growing a second epitaxial material stack in the second recess, the second epitaxial material stack including alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped, a second subset of the second epitaxial material stack being doped; patterning the first epitaxial material stack and the second epitaxial material stack to respectively form first nanowires and second nanowires; and forming a first gate structure around the first nanowires and a second gate structure around the second nanowires.

公开(公告)号：US11114566B2

公开(公告)日：2021-09-07

申请号：US16033256

申请日：2018-07-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Chang Lin ,  Kai-Chieh Yang ,  Chia-Wei Su ,  Jia-Ni Yu ,  Wei-Hao Wu ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/302 ,  H01L23/532 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06

Abstract: A semiconductor device includes a substrate, a first fin, a second fin, a dummy fin, a first metal gate, a second metal gate, and an isolation structure. The first, the second and the dummy fins are on the substrate, and the dummy fin is disposed between the first fin and the second fin. The first metal gate and the second metal gate are over the first fin and the second fin, respectively. The isolation structure is on the dummy fin, and the dummy fin and the isolation structure separate the first metal gate and the second metal gate.

公开(公告)号：US09911848B2

公开(公告)日：2018-03-06

申请号：US14473215

申请日：2014-08-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Carlos H. Diaz ,  Chih-Hao Wang ,  Wai-Yi Lien ,  Kai-Chieh Yang ,  Hao-Ling Tang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/775 ,  H01L21/8238 ,  H01L27/092 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/08

CPC classification number: H01L29/7845 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7843

Abstract: A vertical transistor includes a source-channel-drain structure, a gate and a gate dielectric layer. The source-channel-drain structure includes a source, a drain over the source and a channel between the source and the drain. The gate surrounds a portion of the channel. The gate is configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or the gate is configured to provide tensile strain substantially along the extending direction of the channel when the vertical transistor is a p-channel vertical transistor. In some embodiments, the vertical transistor further includes an ILD configured to provide tensile strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is a p-channel vertical transistor.

公开(公告)号：US20240413020A1

公开(公告)日：2024-12-12

申请号：US18488393

申请日：2023-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsiu Hung ,  Chun-I Tsai ,  Chih-Wei Chang ,  Ming-Hsing Tsai ,  Syun-Ming Jang ,  Wei-Jen Lo ,  Wei-Jung Lin ,  Yu-Ting Wen ,  Kai-Chieh Yang

IPC: H01L21/8238 ,  H01L21/321 ,  H01L27/092 ,  H01L29/66

Abstract: A method includes forming a contact spacer on a sidewall of an inter-layer dielectric, wherein the contact spacer encircles a contact opening, forming a silicide region in the opening and on a source/drain region, depositing an adhesion layer extending into the contact opening, and performing a treatment process, so that the contact spacer is treated. The treatment process is selected from the group consisting of an oxidation process, a carbonation process, and combinations thereof. The method further includes depositing a metal barrier over the adhesion layer, depositing a metallic material to fill the contact opening, and performing a planarization process to remove excess portions of the metallic material over the inter-layer dielectric.