公开(公告)号：US20150162295A1

公开(公告)日：2015-06-11

申请号：US14102548

申请日：2013-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Jen Tseng ,  Wei-Yu Chen ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: H01L23/00 ,  H01L21/768 ,  H01L25/00 ,  H01L25/065 ,  H01L23/528

CPC classification number: H01L24/25 ,  H01L21/743 ,  H01L21/76838 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/535 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A stacked integrated circuit includes multiple tiers vertically connecting together. A multi-layer horizontal connecting structure is fabricated inside a substrate of a tier. Layers of the horizontal connecting structure have different patterns as viewed from above the substrate.

Abstract translation: 堆叠集成电路包括垂直连接在一起的多层。 在层的衬底内制造多层水平连接结构。 水平连接结构的层从衬底上方观察到不同的图案。

公开(公告)号：US11581314B2

公开(公告)日：2023-02-14

申请号：US16723939

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ali Keshavarzi ,  Ta-Pen Guo ,  Shu-Hui Sung ,  Hsiang-Jen Tseng ,  Shyue-Shyh Lin ,  Lee-Chung Lu ,  Chung-Cheng Wu ,  Li-Chun Tien ,  Jung-Chan Yang ,  Ting Yu Chen ,  Min Cao ,  Yung-Chin Hou

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

公开(公告)号：US11437321B2

公开(公告)日：2022-09-06

申请号：US16846690

申请日：2020-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ni-Wan Fan ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Jung-Chan Yang ,  Hsiang-Jen Tseng ,  Lipen Yuan ,  Chi-Yu Lu

IPC: H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H01L23/485 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/535 ,  H01L29/66 ,  H01L27/118

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions within a substrate. A gate structure is over the substrate between the first and second source/drain regions. A middle-end-of-the-line (MEOL) structure is over the second source/drain region. The MEOL structure has a bottommost surface that continuously extends in a first direction from directly contacting a top of the second source/drain region to laterally past an outer edge of the second source/drain region. A conductive structure is on the MEOL structure. A second gate structure is separated from the gate structure by the second source/drain region. The conductive structure continuously extends in a second direction over the MEOL structure and past opposing sides of the second gate structure. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the MEOL structure along through the conductive structure.

公开(公告)号：US20200027854A1

公开(公告)日：2020-01-23

申请号：US16587568

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Jen Tseng ,  Wei-Yu Chen ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/528 ,  H01L25/00 ,  H01L21/768 ,  H01L23/48 ,  H01L21/822 ,  H01L27/06 ,  H01L23/535 ,  H01L21/74 ,  H01L25/07

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first device tier including a first semiconductor substrate having a first plurality of devices. A second semiconductor substrate is formed over the first device tier. A first conductive layer is formed within the second semiconductor substrate, and a second conductive layer is formed within the second semiconductor substrate and over the first conductive layer. The first conductive layer and the second conductive layer have different patterns as viewed from a top-view. A second plurality of devices are formed on the second semiconductor substrate. The first and second conductive layers are configured to electrically couple the first plurality of devices and the second plurality of devices.

公开(公告)号：US20180350743A1

公开(公告)日：2018-12-06

申请号：US16057875

申请日：2018-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ni-Wan Fan ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Jung-Chan Yang ,  Hsiang-Jen Tseng ,  Lipen Yuan ,  Chi-Yu Lu

IPC: H01L23/528 ,  H01L29/66 ,  H01L27/02 ,  H01L21/768 ,  H01L27/088 ,  H01L23/535 ,  H01L21/8234 ,  H01L27/118

CPC classification number: H01L23/5286 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/11807 ,  H01L29/66545

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method is performed by forming a gate structure over a substrate, and selectively implanting the substrate according to the gate structure to form first and second source/drain regions on opposing sides of the gate structure. A first MEOL structure is formed on the first source/drain region and a second MEOL structure is formed on the second source/drain region. The first MEOL structure has a bottommost surface that extends in a first direction from directly over the first source/drain region to laterally past an outermost edge of the first source/drain region. A conductive structure is formed to contact the first MEOL structure and the second MEOL structure. The conductive structure laterally extends from directly over the first MEOL structure to directly over the second MEOL structure along a second direction perpendicular to the first direction.

公开(公告)号：US20180108635A1

公开(公告)日：2018-04-19

申请号：US15846756

申请日：2017-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Jen Tseng ,  Wei-Yu Chen ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/822 ,  H01L23/48 ,  H01L23/528 ,  H01L23/535 ,  H01L21/74 ,  H01L27/06 ,  H01L25/00 ,  H01L25/065 ,  H01L23/522 ,  H01L23/532

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a semiconductor substrate, and an inter-tier interconnecting structure disposed within the semiconductor substrate. The inter-tier interconnect structure includes a first connection point at a lower surface of the inter-tier interconnecting structure and a second connection point at an upper surface of the inter-tier interconnecting structure. The first connection point and the second connection point are not vertically aligned. The inter-tier interconnecting structure includes one or more conductive layers extending between the first and second connection points.

公开(公告)号：US20160336289A1

公开(公告)日：2016-11-17

申请号：US15219357

申请日：2016-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Jen Tseng ,  Wei-Yu Chen ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/528

CPC classification number: H01L24/25 ,  H01L21/743 ,  H01L21/76838 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/535 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-tier interconnecting structure having horizontal components, which is arranged within a semiconductor substrate and configured to electrically couple a first device tier to a second device tier. The integrated chip has a first device tier with a first semiconductor substrate. A first inter-tier interconnecting structure is disposed inside the first semiconductor substrate. The first inter-tier interconnecting structure has a first segment extending in a first direction and a second segment protruding outward from a sidewall of the first segment in a second direction substantially perpendicular to the first direction. A second device tier is electrically coupled to the first device tier by the first inter-tier interconnecting structure.

Abstract translation: 在一些实施例中，本公开涉及具有层间互连结构的集成芯片，其具有水平部件，其布置在半导体衬底内并且被配置为将第一器件层电耦合到第二器件层。 集成芯片具有带有第一半导体衬底的第一器件层。 第一层间互连结构设置在第一半导体衬底的内部。 第一层间互连结构具有沿第一方向延伸的第一段和在基本上垂直于第一方向的第二方向从第一段的侧壁向外突出的第二段。 第二设备层通过第一层间互连结构电耦合到第一设备层。