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    Gallium nitride transistor with a hybrid aluminum oxide layer as a gate dielectric
    12.
    发明授权
    Gallium nitride transistor with a hybrid aluminum oxide layer as a gate dielectric 有权
    具有混合氧化铝层的氮化镓晶体管作为栅极电介质

    公开(公告)号：US09214539B2

    公开(公告)日：2015-12-15

    申请号：US14016328

    申请日：2013-09-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Han-Chin Chiu ,  King-Yuen Wong ,  Cheng-Yuan Tsai ,  Chia-Shiung Tsai ,  Xiaomeng Chen

    IPC: H01L29/10 ,  H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/04

    CPC classification number: H01L29/7787 ,  H01L29/04 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462

    Abstract: Some embodiments of the present disclosure relates to a hybrid gate dielectric layer that has good interface and bulk dielectric properties. Surface traps can degrade device performance and cause large threshold voltage shifts in III-N HEMTs. This disclosure uses a hybrid ALD (atomic layer deposited)-oxide layer which is a combination of H2O-based and O3/O2-based oxide layers that provide both good interface and good bulk dielectric properties to the III-N device. The H2O-based oxide layer provides good interface with the III-N surface, whereas the O3/O2-based oxide layer provides good bulk properties.

    Abstract translation: 本公开的一些实施例涉及具有良好的界面和体介电特性的混合栅极介电层。 表面捕集阱可能会降低器件性能，并在III-N HEMT中引起较大的阈值电压漂移。 本公开使用混合ALD（原子层沉积） - 氧化物层，其是基于H 2 O和O 3 / O 2的氧化物层的组合，其为III-N器件提供良好的界面和良好的体积介电性质。 H 2 O基氧化物层与III-N表面提供良好的界面，而O 3 / O 2基氧化物层提供良好的体积性质。

    HEMT-compatible lateral rectifier structure
    13.
    发明授权
    HEMT-compatible lateral rectifier structure 有权

    公开(公告)号：US11757005B2

    公开(公告)日：2023-09-12

    申请号：US17324471

    申请日：2021-05-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： King-Yuen Wong ,  Ming-Wei Tsai ,  Han-Chin Chiu

    IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L29/861 ,  H01L29/205

    CPC classification number: H01L29/2003 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/861 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/778

    Abstract: The present disclosure, in some embodiments, relates to a semiconductor device. The semiconductor device includes an electron supply layer that is disposed over an upper surface of a semiconductor material and that is laterally arranged between a first conductive terminal and a second conductive terminal. A III-N (III-nitride) semiconductor material is disposed over the electron supply layer. A passivation layer is disposed over the III-N semiconductor material, along a side of the III-N semiconductor material, and over the electron supply layer. An insulating material is arranged over the passivation layer and along opposing sidewalls of the second conductive terminal, and a gate structure is disposed over the passivation layer. The passivation layer has an uppermost surface that is directly coupled to a sidewall of the passivation layer. The insulating material extends along the sidewall of the passivation layer.

    SIDEWALL PASSIVATION FOR HEMT DEVICES
    16.
    发明申请
    SIDEWALL PASSIVATION FOR HEMT DEVICES 有权
    用于HEMT设备的障碍物

    公开(公告)号：US20160351684A1

    公开(公告)日：2016-12-01

    申请号：US15234590

    申请日：2016-08-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

    IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L23/29

    CPC classification number: H01L29/66462 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

    Abstract translation: 本公开的一些实施例涉及一种高电子迁移率晶体管（HEMT），其包括布置在半导体衬底上的异质结结构。 异质结结构包括由作为e-HEMT的沟道区域的第一III族氮化物材料制成的二元III / V半导体层和布置在二元III / V半导体层上的三元III / V半导体层，并制成 的第二III族氮化物材料作为阻挡层。 源极和漏极区域布置在三元III / V半导体层上方并且彼此横向间隔开。 栅极结构布置在异质结结构之上并且布置在源区和漏区之间。 栅极结构由第三III族氮化物材料制成。 第一钝化层围绕栅极结构的侧壁设置并由第四III族氮化物材料制成。

    Sidewall passivation for HEMT devices
    17.
    发明授权
    Sidewall passivation for HEMT devices 有权
    HEMT设备的侧壁钝化

    公开(公告)号：US09425301B2

    公开(公告)日：2016-08-23

    申请号：US14488380

    申请日：2014-09-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

    IPC: H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205 ,  H01L23/29 ,  H01L29/10

    CPC classification number: H01L29/66462 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

    Abstract translation: 本公开的一些实施例涉及一种高电子迁移率晶体管（HEMT），其包括布置在半导体衬底上的异质结结构。 异质结结构包括由作为e-HEMT的沟道区域的第一III族氮化物材料制成的二元III / V半导体层和布置在二元III / V半导体层上的三元III / V半导体层，并制成 的第二III族氮化物材料作为阻挡层。 源极和漏极区域布置在三元III / V半导体层上方并且彼此横向间隔开。 栅极结构布置在异质结结构之上并且布置在源区和漏区之间。 栅极结构由第三III族氮化物材料制成。 第一钝化层围绕栅极结构的侧壁设置并由第四III族氮化物材料制成。

    LOW DAMAGE PASSIVATION LAYER FOR III-V BASED DEVICES
    18.
    发明申请
    LOW DAMAGE PASSIVATION LAYER FOR III-V BASED DEVICES 有权
    基于III-V的器件的低损耗钝化层

    公开(公告)号：US20160240646A1

    公开(公告)日：2016-08-18

    申请号：US14620428

    申请日：2015-02-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Han-Chin Chiu ,  Cheng-Yuan Tsai ,  Ming-Wei Tsai ,  Yao-Wen Chang ,  Wen-Yuan Hsieh

    IPC: H01L29/778 ,  H01L29/51 ,  H01L23/31 ,  H01L23/29 ,  H01L29/66 ,  H01L29/205

    CPC classification number: H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/7787

    Abstract: The present disclosure relates to a structure and method of forming a low damage passivation layer for III-V HEMT devices. In some embodiments, the structure has a bulk buffer layer disposed over a substrate and a device layer of III-V material disposed over the bulk buffer layer. A source region, a drain region and a gate region are disposed above the device layer. The gate region comprises a gate electrode overlying a gate separation layer. A bulk passivation layer is arranged over the device layer, and an interfacial layer of III-V material is disposed between the bulk passivation layer and the device layer in such a way that the source region, the drain region and the gate region extend through the bulk passivation layer and the interfacial layer, to abut the device layer.

    Abstract translation: 本公开内容涉及形成III-V HEMT器件的低损伤钝化层的结构和方法。 在一些实施例中，该结构具有设置在衬底上的体缓冲层和设置在主缓冲层上的III-V材料的器件层。 源极区域，漏极区域和栅极区域设置在器件层上方。 栅极区域包括覆盖栅极分离层的栅电极。 体部钝化层设置在器件层上方，并且III-V材料的界面层以这样的方式设置在体钝化层和器件层之间，使得源极区，漏极区和栅极区延伸穿过 体积钝化层和界面层，以邻接器件层。

    Sidewall Passivation for HEMT Devices
    19.
    发明申请
    Sidewall Passivation for HEMT Devices 有权
    HEMT设备的侧壁钝化

    公开(公告)号：US20150318387A1

    公开(公告)日：2015-11-05

    申请号：US14488380

    申请日：2014-09-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

    IPC: H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205

    CPC classification number: H01L29/66462 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

    Abstract translation: 本公开的一些实施例涉及一种高电子迁移率晶体管（HEMT），其包括布置在半导体衬底上的异质结结构。 异质结结构包括由作为e-HEMT的沟道区域的第一III族氮化物材料制成的二元III / V半导体层和布置在二元III / V半导体层上的三元III / V半导体层，并制成 的第二III族氮化物材料作为阻挡层。 源极和漏极区域布置在三元III / V半导体层上方并且彼此横向间隔开。 栅极结构布置在异质结结构之上并且布置在源区和漏区之间。 栅极结构由第三III族氮化物材料制成。 第一钝化层围绕栅极结构的侧壁设置并由第四III族氮化物材料制成。

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