公开(公告)号：US20200105535A1

公开(公告)日：2020-04-02

申请号：US16539225

申请日：2019-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung LIN ,  Jung-Hung CHANG ,  Shih-Cheng CHEN ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L21/285 ,  H01L29/66 ,  H01L21/764 ,  H01L29/06 ,  H01L29/45 ,  H01L29/78

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a first dielectric layer over the base portion and a first sidewall of the fin portion. The method includes forming a first spacer layer over the first dielectric layer. The method includes forming a first dielectric fin over the first spacer layer. The method includes forming an epitaxial structure over the fin portion, wherein a void is surrounded by the epitaxial structure, the first dielectric layer, and the first spacer layer. The method includes removing the first spacer layer between the epitaxial structure and the first dielectric fin. The method includes forming a silicide layer over the epitaxial structure, wherein a first lower portion of the silicide layer covers a lower surface of the epitaxial structure and is in the void.

公开(公告)号：US20180350984A1

公开(公告)日：2018-12-06

申请号：US16049358

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Carlos H. DIAZ ,  Chun-Hsiung LIN ,  Huicheng CHANG ,  Syun-Ming JANG ,  Chien-Hsun WANG ,  Mao-Lin HUANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/775 ,  H01L29/66 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/778 ,  H01L29/165 ,  H01L29/51

CPC classification number: H01L29/7842 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78696

Abstract: In a method of manufacturing a semiconductor device, a support layer is formed over a substrate. A patterned semiconductor layer made of a first semiconductor material is formed over the support layer. A part of the support layer under a part of the semiconductor layer is removed, thereby forming a semiconductor wire. A semiconductor shell layer made of a second semiconductor material different from the first semiconductor material is formed around the semiconductor wire.

公开(公告)号：US20160079358A1

公开(公告)日：2016-03-17

申请号：US14488082

申请日：2014-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Gerben DOORNBOS ,  Chun-Hsiung LIN ,  Chien-Hsun WANG ,  Carlos H. DIAZ

IPC: H01L29/06 ,  H01L21/48 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/823418 ,  H01L29/0676 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor structure, and methods for forming the semiconductor device are provided. In various embodiments, the semiconductor device includes a substrate, source/drain regions over the substrate, a plurality of nanowires over the substrate and sandwiched by the source/drain regions, a gate dielectric layer surrounding the plurality of nanowires, and a gate layer surrounding the gate dielectric layer.

Abstract translation: 提供半导体结构，以及形成半导体器件的方法。 在各种实施例中，半导体器件包括衬底，衬底上的源极/漏极区域，衬底上的多个纳米线并被源极/漏极区域夹持，围绕多个纳米线的栅极介电层和围绕 栅介质层。

公开(公告)号：US20160043173A1

公开(公告)日：2016-02-11

申请号：US14454645

申请日：2014-08-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yung-Sung YEN ,  Huan-Just LIN ,  Chun-Hsiung LIN ,  Chi-Cheng HUNG

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/42392 ,  H01L29/0676 ,  H01L29/78642 ,  H01L29/78696

Abstract: A semiconductor structure, a semiconductor device, and a method for forming the semiconductor device are provided. In various embodiments, the method for forming the semiconductor device includes forming transistors on a substrate. Forming each transistor includes forming a doped region on the substrate. A nanowire is formed protruding from the doped region. An interlayer dielectric layer is deposited over the doped region. A dielectric layer is deposited over the interlayer dielectric layer and surrounding each of the nanowires. A first gate layer is deposited over the dielectric layer. The dielectric layer and first gate layer are etched to expose portions of the nanowires and the interlayer dielectric layer. A second gate layer is formed over the exposed interlayer dielectric layer and surrounding the first gate layer. Then, the second gate layer was patterned to remove the second gate layer on the interlayer dielectric layer between the transistors.

Abstract translation: 提供半导体结构，半导体器件和用于形成半导体器件的方法。 在各种实施例中，用于形成半导体器件的方法包括在衬底上形成晶体管。 形成每个晶体管包括在衬底上形成掺杂区域。 形成从掺杂区域突出的纳米线。 在掺杂区域上沉积层间电介质层。 介电层沉积在层间电介质层上并围绕每个纳米线。 在电介质层上沉积第一栅极层。 蚀刻介电层和第一栅极层以暴露纳米线和层间介电层的部分。 第二栅极层形成在暴露的层间介电层上并围绕第一栅极层。 然后，对第二栅极层进行图案化以去除晶体管之间的层间电介质层上的第二栅极层。

公开(公告)号：US20240136418A1

公开(公告)日：2024-04-25

申请号：US18403495

申请日：2024-01-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Cheng CHEN ,  Chun-Hsiung LIN ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L21/762 ,  H01L21/764 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L29/40

CPC classification number: H01L29/41791 ,  H01L21/76232 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L29/401

Abstract: A device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The source/drain epitaxial structure is over the active region and adjacent the gate structure. The epitaxial layer is over the source/drain epitaxial structure. The metal alloy layer is over the epitaxial layer. The contact is over the metal alloy layer. The contact etch stop layer lines sidewalls of the source/drain epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.

公开(公告)号：US20210376095A1

公开(公告)日：2021-12-02

申请号：US16886572

申请日：2020-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Cheng CHEN ,  Chun-Hsiung LIN ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L21/762 ,  H01L21/764 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L21/8238

Abstract: A device includes an active region, a gate structure, an epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The epitaxial structure is above the active region and adjacent the gate structure. The epitaxial layer is above the epitaxial structure. The metal alloy layer is above the epitaxial layer. The contact is above the metal alloy layer. The contact etch stop layer lines sidewalls of the epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.

公开(公告)号：US20210083090A1

公开(公告)日：2021-03-18

申请号：US16571817

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Han WANG ,  Pei-Hsun WANG ,  Chun-Hsiung LIN ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08

Abstract: Methods for manufacturing a semiconductor structure is provided. The method for manufacturing the semiconductor structure includes forming nanowire structures over a substrate and forming a gate structure across nanowire structures. The method for manufacturing the semiconductor structure also includes forming a source/drain structure adjacent to the gate structure and forming a Si layer over the source/drain structure. The method for manufacturing the semiconductor structure also includes forming a SiGe layer over the Si layer and oxidizing the SiGe layer to form an oxide layer. The method for manufacturing the semiconductor structure also includes forming a contact through the Si layer over the source/drain structure.

公开(公告)号：US20210082966A1

公开(公告)日：2021-03-18

申请号：US16571751

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang LIN ,  Chun-Hsiung LIN ,  Chih-Hao WANG

IPC: H01L27/12 ,  H01L21/308 ,  H01L29/78 ,  H01L29/06

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack over a substrate. The substrate has a base and a first fin structure over the base, and the first gate stack wraps around a first upper portion of the first fin structure. The method includes partially removing the first fin structure, which is not covered by the first gate stack. The method includes forming a first mask layer over a first sidewall of the first fin structure. The method includes forming a first stressor over a second sidewall of the first fin structure while the first mask layer covers the first sidewall. The first sidewall is opposite to the second sidewall. The method includes removing the first mask layer. The method includes forming a dielectric layer over the base and the first stressor. The dielectric layer covers the first sidewall.

公开(公告)号：US20200373405A1

公开(公告)日：2020-11-26

申请号：US16988608

申请日：2020-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Lun CHEN ,  Bau-Ming WANG ,  Chun-Hsiung LIN

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/3115

Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a first gate spacer, and an epitaxy structure. The substrate has a semiconductor fin. The isolation structure is over the substrate and laterally surrounds the semiconductor fin. The first gate structure is over the substrate and crosses the semiconductor fin. The first gate spacer extends along a sidewall of the first gate structure, in which the first gate spacer has a stepped sidewall distal to the first gate structure. The epitaxy structure is over the semiconductor fin, in which the epitaxy structure is in contact with the stepped sidewall of the first gate spacer.

公开(公告)号：US20200091309A1

公开(公告)日：2020-03-19

申请号：US16178928

申请日：2018-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung LIN ,  Pei-Hsun WANG ,  Chih-Chao CHOU ,  Chia-Hao CHANG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L21/764 ,  H01L21/768 ,  H01L21/033 ,  H01L21/8234 ,  H01L27/088

Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate structure over a substrate, forming a disposable spacer on a sidewall of the gate structure, and forming a source region and a drain region at opposite sides of the gate structure. The method also includes depositing an interlayer dielectric layer around the disposable spacer, and forming a first hard mask on the interlayer dielectric layer. The method further includes removing an upper portion of the gate structure, and removing the disposable spacer to form a trench between the gate structure and the interlayer dielectric layer. In addition, the method includes sealing the trench to form an air-gap spacer, and forming a second hard mask on the gate structure.