公开(公告)号：US20200343140A1

公开(公告)日：2020-10-29

申请号：US16924546

申请日：2020-07-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pei-Hsun WANG ,  Chun-Hsiung LIN ,  Chih-Hao WANG ,  Chih-Chao CHOU

IPC: H01L21/8234 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L21/308

Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a fin protruding from a substrate and forming an isolation structure surrounding the fin. The method also includes epitaxially growing channel fins on sidewalls of the fin over the isolation structure and etching the fin to form a space between the channel fins. The method further includes forming a gate structure to fill the space between the channel fins.

公开(公告)号：US20200135571A1

公开(公告)日：2020-04-30

申请号：US16284113

申请日：2019-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun WANG ,  Chun-Hsiung LIN ,  Chih-Hao WANG ,  Chih-Chao CHOU

IPC: H01L21/8234 ,  H01L21/308 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088

Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin protruding from a substrate, and forming a disposable mandrel fin on the fin. The method also includes epitaxially growing channel fins on sidewalls of the disposable mandrel fin. The method further includes removing the disposable mandrel fin to form a space between the channel fins, and forming a gate structure to fill the space between the channel fins and to wrap the channel fins. In addition, the method includes forming source and drain structures on opposite sides of the gate structure.

公开(公告)号：US20190067442A1

公开(公告)日：2019-02-28

申请号：US15801171

申请日：2017-11-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung LIN ,  Chia-Hao CHANG ,  Chih-Hao WANG ,  Wai-Yi LIEN ,  Chih-Chao CHOU ,  Pei-Yu WANG

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/764 ,  H01L29/78

Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.

公开(公告)号：US20230009640A1

公开(公告)日：2023-01-12

申请号：US17738928

申请日：2022-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao CHOU ,  Yi-Hsun CHIU ,  Shang-Wen CHANG ,  Ching-Wei TSAI ,  Chih-Hao WANG

IPC: H01L21/66 ,  H01L23/528 ,  H01L23/522 ,  G01R31/3183

Abstract: Semiconductor devices and methods are provided which facilitate performing physical failure analysis (PFA) testing from a backside of the devices. In at least one example, a device is provided that includes a semiconductor device layer including a plurality of diffusion regions. A first interconnection structure is disposed on a first side of the semiconductor device layer, and the first interconnection structure includes at least one electrical contact. A second interconnection structure is disposed on a second side of the semiconductor device layer, and the second interconnection structure includes a plurality of backside power rails. Each of the backside power rails at least partially overlaps a respective diffusion region of the plurality of diffusion regions and defines openings which expose portions of the respective diffusion region at the second side of the semiconductor device layer.

公开(公告)号：US20200091309A1

公开(公告)日：2020-03-19

申请号：US16178928

申请日：2018-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung LIN ,  Pei-Hsun WANG ,  Chih-Chao CHOU ,  Chia-Hao CHANG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L21/764 ,  H01L21/768 ,  H01L21/033 ,  H01L21/8234 ,  H01L27/088

Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate structure over a substrate, forming a disposable spacer on a sidewall of the gate structure, and forming a source region and a drain region at opposite sides of the gate structure. The method also includes depositing an interlayer dielectric layer around the disposable spacer, and forming a first hard mask on the interlayer dielectric layer. The method further includes removing an upper portion of the gate structure, and removing the disposable spacer to form a trench between the gate structure and the interlayer dielectric layer. In addition, the method includes sealing the trench to form an air-gap spacer, and forming a second hard mask on the gate structure.

公开(公告)号：US20200035805A1

公开(公告)日：2020-01-30

申请号：US16584826

申请日：2019-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung LIN ,  Chia-Hao CHANG ,  Chih-Hao WANG ,  Wai-Yi LIEN ,  Chih-Chao CHOU ,  Pei-Yu WANG

IPC: H01L29/49 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/764 ,  H01L21/28

Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.

公开(公告)号：US20200027960A1

公开(公告)日：2020-01-23

申请号：US16585741

申请日：2019-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung LIN ,  Chia-Hao CHANG ,  Chih-Hao WANG ,  Wai-Yi LIEN ,  Chih-Chao CHOU ,  Pei-Yu WANG

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L21/764 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.