公开(公告)号：US20220215868A1

公开(公告)日：2022-07-07

申请号：US17704644

申请日：2022-03-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC CHINA COMPANY LIMITED

Inventor： Xiu-Li YANG ,  He-Zhou WAN ,  Kuan CHENG ,  Ching-Wei WU

IPC: G11C8/10 ,  G11C8/12 ,  G11C8/14

Abstract: An integrated circuit includes a plurality of memory cells, a first pair of complementary data lines, and a second pair of complementary data lines. The plurality of memory cells include a first array of memory cells and a second array of memory cells. The first pair of complementary data lines are coupled to the first array of memory cells. The second pair of complementary data lines are different from the first pair of complementary data lines and are coupled to the second array of memory cells. A number of memory cells in the first array of memory cells is different from a number of memory cells in the second array of memory cells.

公开(公告)号：US20220171688A1

公开(公告)日：2022-06-02

申请号：US17651595

申请日：2022-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hung CHANG ,  Atul KATOCH ,  Chia-En HUANG ,  Ching-Wei WU ,  Donald G. MIKAN, JR. ,  Hao-I YANG ,  Kao-Cheng LIN ,  Ming-Chien TSAI ,  Saman M.I. ADHAM ,  Tsung-Yung CHANG ,  Uppu Sharath CHANDRA

IPC: G06F11/263 ,  G06F1/10 ,  G06F11/22 ,  G06F11/267 ,  G11C29/12 ,  G11C29/32 ,  G11C29/48

Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.

公开(公告)号：US20200293417A1

公开(公告)日：2020-09-17

申请号：US16888013

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hung CHANG ,  Atul KATOCH ,  Chia-En HUANG ,  Ching-Wei WU ,  Donald G. MIKAN, JR. ,  Hao-I YANG ,  Kao-Cheng LIN ,  Ming-Chien TSAI ,  Saman M.I. ADHAM ,  Tsung-Yung CHANG ,  Uppu Sharath CHANDRA

IPC: G06F11/263 ,  G06F1/10 ,  G06F11/22 ,  G06F11/267 ,  G11C29/48 ,  G11C29/32 ,  G11C29/12

Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.

公开(公告)号：US20190004915A1

公开(公告)日：2019-01-03

申请号：US15700877

申请日：2017-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hung CHANG ,  Atul KATOCH ,  Chia-En HUANG ,  Ching-Wei WU ,  Donald G. MIKAN, JR. ,  Hao-I YANG ,  Kao-Cheng LIN ,  Ming-Chien TSAI ,  Saman M.I ADHAM ,  Tsung-Yung CHANG ,  Uppu Sharath CHANDRA

IPC: G06F11/263 ,  G06F11/22 ,  G06F1/10

Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.

公开(公告)号：US20160019946A1

公开(公告)日：2016-01-21

申请号：US14334935

申请日：2014-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Kuei LIN ,  Hung-Jen LIAO ,  Yen-Huei CHEN ,  Ching-Wei WU

IPC: G11C11/419 ,  G11C5/02 ,  H01L23/522 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  G11C5/06 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1075 ,  G11C7/1096 ,  G11C8/16 ,  G11C11/40 ,  G11C11/412 ,  G11C11/413 ,  G11C11/418 ,  H01L21/768 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-port, three-dimensional bit cell generally comprises a read portion of a cell disposed on a first tier. The read portion comprises a plurality of read port elements. The three-port bit cell further comprises a write portion of the cell disposed on a second tier that is vertically stacked with respect to the first tier. The first and second tiers are coupled using at least one via. The write portion comprises a plurality of write port elements.