公开(公告)号：US20180166280A1

公开(公告)日：2018-06-14

申请号：US15379251

申请日：2016-12-14

Applicant: Texas Instruments Incorporated

Inventor： Prakash Dalpatbhai Dev ,  Fuchao Wang ,  Nicholas Andrew Kusek

IPC: H01L21/225 ,  H01L21/324 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/2251 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/30655 ,  H01L21/31111 ,  H01L21/324

Abstract: In a described example method, semiconductor wafer with a backside silicon nitride layer is encapsulated with a diffusion barrier layer prior to a high temperature anneal greater than about 1000 degrees Celsius. After the high temperature anneal the diffusion barrier layer and the backside silicon nitride layers are stripped.

公开(公告)号：US09899334B1

公开(公告)日：2018-02-20

申请号：US15391742

申请日：2016-12-27

Applicant: Texas Instruments Incorporated

Inventor： Fuchao Wang ,  Prakash Dalpatbhai Dev ,  Dina Rodriguez ,  Dongping Zhang ,  Billy Alan Wofford

IPC: H01L23/544 ,  H01L21/762 ,  H01L21/306 ,  H01L21/311 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L23/544 ,  H01L21/76202 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A method includes: growing a oxide layer on a topside of a semiconductor wafer using a local oxidation of silicon (LOCOS) process; forming a photoresist pattern with an alignment opening on the oxide layer; etching the oxide layer to form a trench in the oxide layer; etching an alignment mark trench into the exposed surface of the semiconductor wafer; depositing a dielectric layer that is one of a silicon nitride material or a silicon oxynitride material; performing an anisotropic plasma etch to remove the dielectric layer from horizontal surfaces on the oxide layer and the alignment mark trench and to form sidewalls from the dielectric layer on vertical sidewalls of the alignment mark trench; growing an alignment mark oxide layer on a bottom surface of the alignment trench; and etching and removing the oxide layer and the alignment mark oxide layer.

公开(公告)号：US20240332369A1

公开(公告)日：2024-10-03

申请号：US18193391

申请日：2023-03-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Fuchao Wang ,  Billy Alan Wofford ,  Ebenezer Eshun ,  Jungwoo Joh ,  Dong Seup Lee

IPC: H01L29/20 ,  H01L21/8252 ,  H01L27/088 ,  H01L29/08 ,  H01L29/40

CPC classification number: H01L29/2003 ,  H01L21/8252 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/402

Abstract: In one example, an integrated circuit comprises a transistor and a metal layer. The transistor has an insulator layer over a substrate that includes gallium nitride (GaN). First and second opening in the insulator layer respectively define a drain region and a source region of the transistor. A gate electrode extends into the insulator layer between the source region and the drain region. The metal layer includes a drain via and a source via. The drain via extends through the first opening to the drain region. The source via extends through the second opening to the source region. A source field plate is in the metal layer. The source field plate extends over the gate electrode and provides a contiguous electrically conductive path to the source region.

公开(公告)号：US20240213333A1

公开(公告)日：2024-06-27

申请号：US18145625

申请日：2022-12-22

Applicant: Texas Instruments Incorporated

Inventor： Fuchao Wang ,  Bill Wofford ,  Jonathan R Garrett ,  Ebenezer Eshun ,  Jungwoo Joh

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/3105 ,  H01L23/495 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/408 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31053 ,  H01L23/4952 ,  H01L23/49562 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

Abstract: A microelectronic device includes a III-N semiconductor layer having a top surface with at least one topological structure in the III-N semiconductor layer. The topological structure may be an opening in the III-N semiconductor layer or a protrusion of the III-N semiconductor layer. The microelectronic device also includes a liner including silicon nitride on the topological structure, contacting the III-N semiconductor layer. The microelectronic device further includes a fill material including silicon nitride on the topological structure on the liner. A top surface of the fill material is planar and parallel to the top surface of the III-N semiconductor layer adjacent to the topological structure.

公开(公告)号：US20230134596A1

公开(公告)日：2023-05-04

申请号：US17514039

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Fuchao Wang ,  James Klawinsky ,  Albert M Estevez ,  Billy A Wofford

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  C23C14/06

Abstract: A method of fabricating an integrated circuit includes forming a titanium nitride layer over a semiconductor substrate in a process chamber and forming a poisoned titanium layer on the titanium nitride layer in the process chamber. Forming the titanium nitride layer includes sputtering titanium from a titanium sputter target using a first nitrogen flow. Forming the poisoned titanium layer includes sputtering titanium from the titanium sputter target using a lower second nitrogen flow. The method also forms an aluminum layer on the poisoned titanium layer.

公开(公告)号：US10403424B2

公开(公告)日：2019-09-03

申请号：US15618353

申请日：2017-06-09

Applicant: Texas Instruments Incorporated

Inventor： Fuchao Wang ,  Yousong Zhang ,  Neal Thomas Murphy ,  Brian Zinn ,  Jonathan P. Davis

IPC: H01F7/06 ,  H01F10/30 ,  H01F17/00 ,  H01F41/04

Abstract: An integrated magnetic device has a magnetic core which includes layers of the magnetic material located in a trench in a dielectric layer. The magnetic material layers are flat and parallel to a bottom of the trench, and do not extend upward along sides of the trench. The integrated magnetic device is formed by forming layers of the magnetic material over the dielectric layer and extending into the trench. A protective layer is formed over the magnetic material layers. The magnetic material layers are removed from over the dielectric layer, leaving the magnetic material layers and a portion of the protective layer in the trench. The magnetic material layers along sides of the trench are subsequently removed. The magnetic material layers along the bottom of the trench provide the magnetic core.

公开(公告)号：US10276787B2

公开(公告)日：2019-04-30

申请号：US15041575

申请日：2016-02-11

Applicant: Texas Instruments Incorporated

Inventor： Dok Won Lee ,  William David French ,  Ricky Alan Jackson ,  Fuchao Wang

IPC: H01L43/12 ,  H01L43/08 ,  H01L27/22

Abstract: An integrated device includes a substrate having a semiconductor surface layer including functional circuitry, a lower metal stack on the semiconductor surface layer, an interlevel dielectric (ILD) layer on the lower metal stack, a top metal layer providing AMR contact pads and bond pads coupled to the AMR contact pads in the ILD layer. An AMR device is above the lower metal stack lateral to the functional circuitry including a patterned AMR stack including a seed layer, an AMR material layer, and a capping layer, wherein the seed layer is coupled to the AMR contact pads by a coupling structure. A protective overcoat (PO layer) is over the AMR stack. There are openings in the PO layer exposing the bond pads.