公开(公告)号：US20210217706A1

公开(公告)日：2021-07-15

申请号：US17011982

申请日：2020-09-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ricky Alan Jackson ,  Erika Lynn Mazotti ,  Sudtida Lavangkul

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/78 ,  H01L23/58 ,  H01L23/31

Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

公开(公告)号：US09748181B1

公开(公告)日：2017-08-29

申请号：US15168479

申请日：2016-05-31

Applicant: Texas Instruments Incorporated

Inventor： Ricky Alan Jackson ,  Sudtida Lavangkul ,  Erika Lynn Mazotti

IPC: H01L23/544 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/562 ,  H01L23/3171 ,  H01L23/528 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/585

Abstract: An example apparatus includes a plurality of scribe streets arranged in rows and columns on the surface of a semiconductor wafer; and a plurality of integrated circuit dies arranged in rows and columns and spaced apart by the scribe streets. Each integrated circuit die includes plurality of active areas; a plurality of insulator layers overlying the active areas; a plurality of conductor layers interspersed with and separated by ones of the insulator layers; and a passivation layer overlying a top portion of the uppermost one of the conductor layers. A scribe seal in a scribe region surrounds the periphery of the integrated circuit dies, the scribe seal covered by the passivation layer; and a crack arrest structure is located surrounding and spaced from the scribe seal, and including an opening in the passivation layer that extends to and exposes the upper surface of the crack arrest structure. Methods are disclosed.

公开(公告)号：US12054385B2

公开(公告)日：2024-08-06

申请号：US17388301

申请日：2021-07-29

Applicant: Texas Instruments Incorporated

Inventor： Ting-Ta Yen ,  Jeronimo Segovia-Fernandez ,  Ricky Alan Jackson ,  Benjamin Cook

IPC: B81B7/00

CPC classification number: B81B7/0048 ,  B81B2201/0271 ,  B81B2203/033

Abstract: A semiconductor system includes a substrate. The substrate has a front side and a back side. A device is formed on the front side of the substrate. A vertical spring is etched in the substrate about the device. A trench is etched in the front side of the substrate about the device. A wall of the trench forms a side of the vertical spring.

公开(公告)号：US20230017047A1

公开(公告)日：2023-01-19

申请号：US17953301

申请日：2022-09-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ricky Alan Jackson ,  Erika Lynn Mazotti ,  Sudtida Lavangkul

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/78 ,  H01L23/58 ,  H01L23/31

Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

公开(公告)号：US20190324097A1

公开(公告)日：2019-10-24

申请号：US16502317

申请日：2019-07-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Erika Lynn Mazotti ,  Dok Won Lee ,  William David French ,  Byron J.R. Shulver ,  Thomas Dyer Bonifield ,  Ricky Alan Jackson ,  Neil Gibson

IPC: G01R33/04 ,  G01R33/00

Abstract: An integrated fluxgate device has a magnetic core disposed over a semiconductor substrate. A first winding is disposed in a first metallization level above and a second metallization level below the magnetic core, and is configured to generate a first magnetic field in the magnetic core. A second winding is disposed in the first and second metallization levels and is configured to generate a second magnetic field in the magnetic core. A third winding is disposed in the first and second metallization levels and is configured to sense a magnetic field in the magnetic core that is the net of the first and second magnetic fields.

公开(公告)号：US09929714B2

公开(公告)日：2018-03-27

申请号：US14251637

申请日：2014-04-13

Applicant: Texas Instruments Incorporated

Inventor： Stuart M. Jacobsen ,  Rick L. Wise ,  Maria Wang ,  Ricky Alan Jackson ,  Nicholas S. Dellas ,  Django Earl Trombley

IPC: H03H9/05 ,  H03H9/02 ,  H03H9/17

CPC classification number: H03H9/02102 ,  H03H9/175

Abstract: The dominant frequency of a solidly mounted resonator (100/280/300/400) is substantially increased by reducing the thickness of each layer of each Bragg acoustic reflector (112/160/224/274) to have a thickness than is substantially equal to one-quarter of the wavelength of a frequency that is a higher harmonic resonant frequency of the fundamental resonant frequency of the solidly mounted resonator (100/280/300/400).

公开(公告)号：US20170345772A1

公开(公告)日：2017-11-30

申请号：US15169700

申请日：2016-05-31

Applicant: Texas Instruments Incorporated

Inventor： Ricky Alan Jackson ,  Erika Lynn Mazotti ,  Sudtida Lavangkul

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/78 ,  H01L23/31 ,  H01L23/544

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L22/32 ,  H01L23/3192 ,  H01L23/585 ,  H01L2223/5446

Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

公开(公告)号：US20170328961A1

公开(公告)日：2017-11-16

申请号：US15152002

申请日：2016-05-11

Applicant: Texas Instruments Incorporated

Inventor： Dok Won Lee ,  William David French ,  Ricky Alan Jackson ,  Ann Margaret Gabrys

IPC: G01R33/04 ,  H01L43/12 ,  H01L27/22

CPC classification number: G01R33/04 ,  H01L27/22 ,  H01L43/12

Abstract: A fluxgate device that includes a first magnetic core and a second magnetic core. The first magnetic core has a first magnetized direction that deviates from a first sense direction by more than 0 degree and less than 90 degrees. The second magnetic core is arranged orthogonally to the first magnetic core. The second magnetic core has a second magnetized direction that deviates from a second sense direction by more than 0 degree and less than 90 degrees.

公开(公告)号：US11782102B2

公开(公告)日：2023-10-10

申请号：US17508706

申请日：2021-10-22

Applicant: Texas Instruments Incorporated

Inventor： Keith Ryan Green ,  Erika Lynn Mazotti ,  William David French ,  Ricky Alan Jackson

IPC: G01R33/07 ,  G01R33/00 ,  H10N52/01 ,  H10N52/80 ,  H10N52/00

CPC classification number: G01R33/072 ,  G01R33/0052 ,  G01R33/077 ,  H10N52/01 ,  H10N52/101 ,  H10N52/80

Abstract: A microelectronic device has a Hall sensor that includes a Hall plate in a semiconductor material. The Hall sensor includes contact regions in the semiconductor material, contacting the Hall plate. The Hall sensor includes an isolation structure with a dielectric material contacting the semiconductor material, on at least two opposite sides of each of the contact regions. The isolation structure is laterally separated from the contact regions by gaps. The Hall sensor further includes a conductive spacer over the gaps, the conductive spacer being separated from the semiconductor material by an insulating layer.

公开(公告)号：US11515266B2

公开(公告)日：2022-11-29

申请号：US17011982

申请日：2020-09-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ricky Alan Jackson ,  Erika Lynn Mazotti ,  Sudtida Lavangkul

IPC: H01L23/544 ,  H01L23/00 ,  H01L21/66 ,  H01L21/78 ,  H01L23/58 ,  H01L23/31

Abstract: An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.