公开(公告)号：US12166054B2

公开(公告)日：2024-12-10

申请号：US18446572

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Lin Chen ,  Yi-Shin Chu ,  Yin-Kai Liao ,  Sin-Yi Jiang ,  Kuan-Chieh Huang ,  Jhy-Jyi Sze

IPC: H01L27/146 ,  H01L31/105

Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.

公开(公告)号：US11908900B2

公开(公告)日：2024-02-20

申请号：US17869885

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yin-Kai Liao ,  Sin-Yi Jiang ,  Hsiang-Lin Chen ,  Yi-Shin Chu ,  Po-Chun Liu ,  Kuan-Chieh Huang ,  Jyh-Ming Hung ,  Jen-Cheng Liu

IPC: H01L29/10 ,  H01L29/167 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/1087 ,  H01L29/167 ,  H01L29/4933 ,  H01L29/6659

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.

公开(公告)号：US11855237B2

公开(公告)日：2023-12-26

申请号：US18151828

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jhy-Jyi Sze ,  Sin-Yi Jiang ,  Yi-Shin Chu ,  Yin-Kai Liao ,  Hsiang-Lin Chen ,  Kuan-Chieh Huang

IPC: H01L31/112 ,  H01L31/18 ,  H01L27/146 ,  H01L29/808 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L31/1129 ,  H01L27/14679 ,  H01L29/66893 ,  H01L29/808 ,  H01L31/112 ,  H01L31/1804 ,  H01L31/1864 ,  H01L29/1066

Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.

公开(公告)号：US20210296258A1

公开(公告)日：2021-09-23

申请号：US17340425

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Yu Chien ,  Chien-Hsien Tseng ,  Dun-Nian Yaung ,  Nai-Wen Cheng ,  Pao-Tung Chen ,  Yi-Shin Chu ,  Yu-Yang Shen

IPC: H01L23/552 ,  H01L23/538 ,  H01L29/06 ,  H01L21/768 ,  H01L21/762

Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components. Further, the shield structure substantially covers the second electronic component and/or would substantially cover the first electronic component if the semiconductor packaging device was flipped vertically.

公开(公告)号：US10727164B2

公开(公告)日：2020-07-28

申请号：US16228585

申请日：2018-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Ching-Chun Wang ,  Kuan-Chieh Huang ,  Hsing-Chih Lin ,  Yi-Shin Chu

IPC: H01L23/52 ,  H01L23/48 ,  H01L21/48 ,  H01L21/02 ,  H01L23/522 ,  H01L21/768

Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate having an active side, an interconnect layer in proximity to the active side of the semiconductor substrate, and a through substrate via extending from the semiconductor substrate to a first metal layer of the interconnect layer. The TSV being wider than the continuous metal feature. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.

公开(公告)号：US09123617B2

公开(公告)日：2015-09-01

申请号：US14531820

申请日：2014-11-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Hsun Wan ,  Yi-Shin Chu ,  Szu-Ying Chen ,  Pao-Tung Chen ,  Jen-Cheng Liu ,  Dun-Nian Yaung

IPC: H01L21/00 ,  H01L27/146 ,  H01L31/0352 ,  H01L31/18

CPC classification number: H01L27/14632 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689 ,  H01L27/1469 ,  H01L31/022466 ,  H01L31/035218 ,  H01L31/03762 ,  H01L31/18 ,  H04N5/378

Abstract: A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode.

Abstract translation: 一种器件包括在其中形成有升高的光电二极管的图像传感器芯片，以及下面并结合到图像传感器芯片的器件芯片。 器件芯片具有电连接到升高的光电二极管的读出电路。

公开(公告)号：US20240120639A1

公开(公告)日：2024-04-11

申请号：US18448045

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Hsiang Huang ,  Fong-Yuan Chang ,  Tsui-Ping Wang ,  Yi-Shin Chu

IPC: H01Q1/22 ,  H01L23/66 ,  H01Q1/50 ,  H01Q23/00

CPC classification number: H01Q1/2283 ,  H01L23/66 ,  H01Q1/50 ,  H01Q23/00

Abstract: A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.

公开(公告)号：US20230369293A1

公开(公告)日：2023-11-16

申请号：US18358186

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Yi-Shin Chu ,  Ping-Tzu Chen ,  Che-Wei Chen

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53228 ,  H01L23/53257 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05624 ,  H01L2224/05684 ,  H01L2224/08146 ,  H01L2225/06541

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

公开(公告)号：US20230343885A1

公开(公告)日：2023-10-26

申请号：US17835049

申请日：2022-06-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Lin Chen ,  Sin-Yi Jiang ,  Sung-Wen Huang Chen ,  Yin-Kai Liao ,  Jung-I Lin ,  Yi-Shin Chu ,  Kuan-Chieh Huang

IPC: H01L31/103 ,  H01L31/0288 ,  H01L31/18

CPC classification number: H01L31/103 ,  H01L31/0288 ,  H01L31/1804

Abstract: Image sensors and methods of forming the same are provided. An image sensor according to the present disclosure includes a silicon substrate, a germanium region disposed in the silicon substrate, a doped semiconductor isolation layer disposed between the silicon substrate and the germanium region, a heavily p-doped region disposed on the germanium region, a heavily n-doped region disposed on the silicon substrate, a first n-type well disposed immediately below the germanium region, a second n-type well disposed immediately below the heavily n-doped region, and a deep n-type well disposed below and in contact with the first n-type well and the second n-type well.

公开(公告)号：US11756936B2

公开(公告)日：2023-09-12

申请号：US17703088

申请日：2022-03-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Yi-Shin Chu ,  Ping-Tzu Chen ,  Che-Wei Chen

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53228 ,  H01L23/53257 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05624 ,  H01L2224/05684 ,  H01L2224/08146 ,  H01L2225/06541

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.