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28 条记录 (耗时 0.024 秒)

    Three dimensional integrated circuit electrostatic discharge protection and prevention test interface
    12.
    发明授权
    Three dimensional integrated circuit electrostatic discharge protection and prevention test interface 有权

    公开(公告)号：US11229109B2

    公开(公告)日：2022-01-18

    申请号：US16851873

    申请日：2020-04-17

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Mill-Jer Wang ,  Ching-Nen Peng ,  Hung-Chih Lin ,  Hao Cheng

    IPC分类号： H02H9/00 ,  H05F3/02 ,  H02H9/04 ,  G01R1/073 ,  G01R1/36 ,  H05K1/11 ,  H05K1/18

    摘要： The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.

    Test circuit and method
    14.
    发明授权
    Test circuit and method 有权

    公开(公告)号：US09891266B2

    公开(公告)日：2018-02-13

    申请号：US14189112

    申请日：2014-02-25

    申请人： Taiwan Semiconductor Manufacturing CO., LTD.

    发明人： Mill-Jer Wang ,  Ching-Nen Peng ,  Hung-Chih Lin ,  Sen-Kuei Hsu ,  Chuan-Ching Wang ,  Hao Chen

    IPC分类号： G01R31/265 ,  G01R31/302

    CPC分类号： G01R31/265 ,  G01R31/3025

    摘要： A method is disclosed that includes the operations outlined below. For a plurality of dies on a test fixture, an antenna distance between each of first antennas of one of the dies and every one of first antennas of the other dies is determined. The dies are categorized into die groups, wherein the antenna distance between each of the first antennas of one of the dies in one of the die groups and every one of the first antennas of the other dies in the same one of the die groups is larger than an interference threshold. Test processes are sequentially performed on the die groups. Each of the test processes is performed according to signal transmissions between the first antennas and second antennas of the under-test device each positionally corresponds to one of the first antennas.

    Test circuit and method
    15.
    发明授权
    Test circuit and method 有权

    公开(公告)号：US09640447B2

    公开(公告)日：2017-05-02

    申请号：US14186107

    申请日：2014-02-21

    申请人： Taiwan Semiconductor Manufacturing CO., LTD.

    发明人： Mill-Jer Wang ,  Ching-Nen Peng ,  Hung-Chih Lin ,  Hao Chen ,  Chung-Han Huang

    IPC分类号： G01R1/04 ,  G01R31/26 ,  H01L21/66 ,  G01R31/28

    CPC分类号： H01L22/14 ,  G01R31/2889

    摘要： A circuit is disclosed that includes a signal-forcing path, a discharging path, a contact probe, a monitoring probe and a switch module. The signal-forcing path is connected to a signal source. The discharging path is connected to a discharging voltage terminal. The contact probe contacts a pad module of an under-test device. The monitoring probe generates a monitored voltage associated with the pad module. The switch module is operated in a discharging mode to connect the contact probe to the discharging path when the monitored voltage does not reach a threshold voltage such that the under-test device is discharged and is operated in an operation mode to connect the contact probe to the signal-forcing path when the monitored voltage reaches the threshold voltage such that a signal generated by the signal source is forced to the under-test device.

    Structure and method for testing stacked CMOS structure
    17.
    发明授权
    Structure and method for testing stacked CMOS structure 有权
    堆叠CMOS结构测试的结构和方法

    公开(公告)号：US09568543B2

    公开(公告)日：2017-02-14

    申请号：US14062935

    申请日：2013-10-25

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Mill-Jer Wang ,  Ching-Nen Peng ,  Hung-Chih Lin ,  Hao Chen

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  H01L21/66 ,  H01L27/06

    CPC分类号： G01R31/2851 ,  G01R31/2884 ,  G01R31/318513 ,  H01L22/34 ,  H01L27/0688

    摘要： A test structure is provided for testing a semiconductor structure having a plurality of tiers. The test structure includes at least one conductive loop. Each respective conductive loop has ends defining at least one opening between the ends, and is embedded inside one or more of the plurality of tiers in the semiconductor structure. The test structure also includes at least two test pads on each respective conductive loop. The at least two test pads are connected with respective ends of each respective conductive loop. The test structure is configured to permit detection of defects within each of the plurality of tiers in the semiconductor structure if the defects exist, using a testing apparatus.

    摘要翻译： 提供了一种用于测试具有多个层的半导体结构的测试结构。 测试结构包括至少一个导电回路。 每个相应的导电回路具有限定端部之间的至少一个开口的端部，并且被嵌入在半导体结构中的多个层中的一个或多个层内。 测试结构还包括在每个相应的导电回路上的至少两个测试焊盘。 至少两个测试焊盘与每个相应的导电回路的相应端连接。 如果存在缺陷，则使用测试装置，将测试结构配置为允许检测半导体结构中的多个层的每一层内的缺陷。

    Test-yield improvement devices for high-density probing techniques and method of implementing the same
    18.
    发明授权
    Test-yield improvement devices for high-density probing techniques and method of implementing the same 有权
    用于高密度探测技术的测试产量改进装置及其实施方法

    公开(公告)号：US09354254B2

    公开(公告)日：2016-05-31

    申请号：US13865243

    申请日：2013-04-18

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Mill-Jer Wang ,  Ching-Nen Peng ,  Hung-Chih Lin ,  Wei-Hsun Lin ,  Sen-Kuei Hsu ,  De-Jian Liu

    IPC分类号： G01R31/20 ,  G01R1/073 ,  G01R1/067

    CPC分类号： G01R1/07314 ,  G01R1/06794 ,  G01R1/07364

    摘要： A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.

    摘要翻译： 公开了一种具有减小探针卡翘曲的测试装置和减少测试装置的探针卡翘曲的方法。 测试装置可以包括测试头和与测试头相对的平台，其中测试头和平台相对于彼此移动以使样本与测试装置的探测尖端接触。 测试头可以包括探针卡印刷电路板，加强件，不连续的支撑件和多个探测尖端。 加强件可以联接到并加强探针卡。 不连续的支撑件可以从探针卡延伸到加强件，并且可以包括从加强件延伸到探针卡的至少一个未填充的空隙。 多个探测尖端可以从测试头的远端延伸。

    Integrated fan-out wafer architecture and test method
    19.
    发明授权
    Integrated fan-out wafer architecture and test method 有权
    集成扇出晶圆架构和测试方法

    公开(公告)号：US09234940B2

    公开(公告)日：2016-01-12

    申请号：US14151850

    申请日：2014-01-10

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Mill-Jer Wang ,  Ching-Nen Peng ,  Hung-Chih Lin ,  Hao Chen

    IPC分类号： G01R31/28 ,  G01R31/3177 ,  G01R31/317

    CPC分类号： G01R31/3177 ,  G01R31/31723 ,  G01R31/318533 ,  G01R31/318538

    摘要： A fan-out wafer comprises a first IC die having at least a first boundary scan cell (BSC) and a second BSC. The first BSC is coupled to a first demultiplexer. The second BSC is coupled to a first pad. A second IC die has at least a third BSC coupled to a second demultiplexer, and a second pad connected to the first pad. A first master path connects the first demultiplexer to the second demultiplexer. A first slave path connects the first demultiplexer to the second demultiplexer. The first pad and second pad are located between the first master path and the first slave path.

    摘要翻译： 扇出晶片包括具有至少第一边界扫描单元（BSC）和第二BSC的第一IC管芯。 第一BSC耦合到第一解复用器。 第二BSC耦合到第一焊盘。 第二IC管芯具有耦合到第二解复用器的至少第三BSC和连接到第一焊盘的第二焊盘。 第一主路径将第一解复用器连接到第二解复用器。 第一从路径将第一解复用器连接到第二解复用器。 第一焊盘和第二焊盘位于第一主路径和第一从属路径之间。