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公开(公告)号：US20210099148A1
公开(公告)日：2021-04-01
申请号：US16586153
申请日：2019-09-27
Applicant: Silicon Laboratories Inc.
Inventor： Ruifeng Sun , Francesco Barale , Vinod Jayakumar , Sherry Xiaohong Wu , Mustafa H. Koroglu , Essam S. Atalla
Abstract: Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. For disclosed embodiments, a filter circuit is coupled between a first internal node and a connection pad for an integrated circuit. The filter circuit includes a first inductance, a variable capacitance, and a second inductance. The capacitance amount for the variable capacitance is controlled to tune filtering for the filter circuit to a harmonic of a frequency for a transmit output signal. A power amplifier outputs the transmit output signal to the connection pad without passing through the filter circuit. The filter circuit filters the harmonic of the frequency for the transmit output signal, shunting harmonic current to ground. For one embodiment, the filtered harmonic is a third harmonic of the transmit frequency. For one embodiment, the transmit output signal has an output power greater than or equal to 15 dBm.
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Patent Agency Ranking
公开(公告)号：US20170359076A1
公开(公告)日：2017-12-14
申请号：US15370742
申请日：2016-12-06
Applicant: Silicon Laboratories Inc.
Inventor： Aslamali A. Rafi , Rangakrishnan Srinivasan , Francesco Barale
CPC classification number: H03L7/183 , H03L7/0891 , H03L7/099 , H03L7/0995 , H03L7/18 , H03L2207/06
Abstract: An apparatus includes a signal generator. The signal generator includes a voltage controlled oscillator (VCO) coupled to provide an output signal having a frequency. The signal generator further includes an asymmetric divider coupled to receive the output signal of the VCO and to provide an output signal. The output signal of the asymmetric divider has a frequency that is half the frequency of the output signal of the VCO. The asymmetric divider presents a balanced load to the VCO.
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公开(公告)号：US12047042B2
公开(公告)日：2024-07-23
申请号：US17539090
申请日：2021-11-30
Applicant: Silicon Laboratories Inc.
Inventor： Diptendu Ghosh , Mustafa H. Koroglu , Dayasagar Gaade , Francesco Barale
CPC classification number: H03F3/217 , H03L7/0812 , H03F2200/165 , H03K19/20
Abstract: A switching power amplifier with harmonic suppression including a polyphase converter and a power amplifier stage. The polyphase converter converts a frequency or phase modulated input signal into a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when high, and a negative 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when low. The power amplifier stage includes first and second branches coupled between upper and lower nodes, each including series-coupled P-channel and N-channel transistors forming an intermediate output node. The transistors of the first branch are controlled by the 50% duty cycle signal, and the transistors of the second branch are controlled by the positive and negative 25% duty cycle signals. The first and second branches generate output currents that are superimposed with each other to suppress third and fifth harmonics.
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公开(公告)号：US20230170855A1
公开(公告)日：2023-06-01
申请号：US17539090
申请日：2021-11-30
Applicant: Silicon Laboratories Inc.
Inventor： Diptendu Ghosh , Mustafa H. Koroglu , Dayasagar Gaade , Francesco Barale
CPC classification number: H03F3/217 , H03L7/0812 , H03F2200/165 , H03K19/20
Abstract: A switching power amplifier with harmonic suppression including a polyphase converter and a power amplifier stage. The polyphase converter converts a frequency or phase modulated input signal into a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when high, and a negative 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when low. The power amplifier stage includes first and second branches coupled between upper and lower nodes, each including series-coupled P-channel and N-channel transistors forming an intermediate output node. The transistors of the first branch are controlled by the 50% duty cycle signal, and the transistors of the second branch are controlled by the positive and negative 25% duty cycle signals. The first and second branches generate output currents that are superimposed with each other to suppress third and fifth harmonics.
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公开(公告)号：US10256854B1
公开(公告)日：2019-04-09
申请号：US15875278
申请日：2018-01-19
Applicant: Silicon Laboratories Inc.
Inventor： Rangakrishnan Srinivasan , Sriharsha Vasadi , Zhongda Wang , Mustafa H. Koroglu , John M. Khoury , Aslamali A. Rafi , Michael S. Johnson , Francesco Barale , Sherry Xiaohong Wu
Abstract: In an embodiment, an apparatus includes: a transmit circuit to upconvert a baseband signal to a first differential radio frequency (RF) signal, the transmit circuit to convert the first differential RF signal to a first single-ended RF signal; a duty cycle correction circuit coupled to the transmit circuit to receive the first single-ended RF signal and compensate for a duty cycle variation in the first single-ended RF signal to output a duty cycle-corrected RF signal; a conversion circuit to convert the duty cycle-corrected RF signal to a second differential RF signal; and an interface circuit to transfer the second differential RF signal from a first ground domain to a second ground domain.
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公开(公告)号：US09966965B2
公开(公告)日：2018-05-08
申请号：US15370742
申请日：2016-12-06
Applicant: Silicon Laboratories Inc.
Inventor： Aslamali A. Rafi , Rangakrishnan Srinivasan , Francesco Barale
CPC classification number: H03L7/183 , H03L7/0891 , H03L7/099 , H03L7/0995 , H03L7/18 , H03L2207/06
Abstract: An apparatus includes a signal generator. The signal generator includes a voltage controlled oscillator (VCO) coupled to provide an output signal having a frequency. The signal generator further includes an asymmetric divider coupled to receive the output signal of the VCO and to provide an output signal. The output signal of the asymmetric divider has a frequency that is half the frequency of the output signal of the VCO. The asymmetric divider presents a balanced load to the VCO.
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