公开(公告)号：US12113109B2

公开(公告)日：2024-10-08

申请号：US17313638

申请日：2021-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin Kim ,  Juhun Park ,  Deokhan Bae ,  Myungyoon Um ,  Yuri Lee ,  Inyeal Lee ,  Yoonyoung Jung ,  Sooyeon Hong

IPC: H01L29/417 ,  H01L27/092

CPC classification number: H01L29/41791 ,  H01L27/0924

Abstract: A semiconductor device includes a first active (e.g., PMOSFET) region and an adjacent second active (e.g., NMOSFET) region on a substrate, a device isolation layer on the substrate and defining a first active pattern on the first active region and a second active pattern on the second active region, a gate electrode crossing the first and second active patterns, a first source/drain pattern and a second source/drain pattern adjacent to a side of the gate electrode, an interlayer insulating layer on the gate electrode, a first active contact penetrating the interlayer insulating layer to connect the first source/drain pattern and a second active contact penetrating the interlayer insulating layer to connect the second source/drain pattern and a buffer layer provided in an upper region of the interlayer insulating layer and interposed between the first active contact and the second active contact, wherein the buffer layer includes a material having etch selectivity with respect to the interlayer insulating layer.

公开(公告)号：US20240324165A1

公开(公告)日：2024-09-26

申请号：US18678213

申请日：2024-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan Bae ,  Juhun Park ,  Yuri Lee ,  Yoonyoung Jung ,  Sooyeon Hong

IPC: H10B10/00 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H10B10/125 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor memory device includes an active pattern on a substrate, the active pattern including a source/drain pattern in an upper portion thereof, a gate electrode on the active pattern and extended in a first direction, the gate electrode and the source/drain pattern adjacent to each other in a second direction that crosses the first direction, and a shared contact coupled to the source/drain pattern and the gate electrode to electrically connect the source/drain pattern and the gate electrode. The shared contact includes active and gate contacts, which are electrically connected to the source/drain pattern and the gate electrode, respectively. The gate contact includes a body portion coupled to the gate electrode and a protruding portion, which protrudes from the body portion in the second direction and extends into and buried in the active contact.

公开(公告)号：US11646316B2

公开(公告)日：2023-05-09

申请号：US17700590

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokhan Bae ,  Sungmin Kim ,  Juhun Park ,  Yuri Lee ,  Yoonyoung Jung ,  Sooyeon Hong

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L29/6656 ,  H01L29/7851

Abstract: Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.

公开(公告)号：US20230120532A1

公开(公告)日：2023-04-20

申请号：US17717268

申请日：2022-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sooyeon Hong ,  Deokhan Bae ,  Juhun Park ,  Yuri Lee ,  Yoonyoung Jung

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device of the disclosure includes an active pattern extending on a substrate in a first direction, a gate structure extending on the active pattern in a second direction intersecting the first direction, a source/drain region disposed on at least one side of the gate structure, a source/drain contact connected to the source/drain region, and a contact insulating layer disposed on the source/drain contact. The contact insulating layer includes at least one air gap. The air gap is disposed on an upper surface of the source/drain contact.

公开(公告)号：US20190304973A1

公开(公告)日：2019-10-03

申请号：US16444683

申请日：2019-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin Kim ,  Jisu Kang ,  Jaehyun Park ,  Heonjong Shin ,  Yuri Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/10

Abstract: A semiconductor device includes a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other, an isolation pattern disposed between the first and second active regions, a semiconductor extension layer disposed between the first and second active regions, a first source/drain semiconductor layer disposed on the first active region, and a second source/drain semiconductor layer disposed on the second active region. The facing side surfaces of the first and second active regions are closer to the semiconductor extension layer than the isolation pattern.