公开(公告)号：US20240138143A1

公开(公告)日：2024-04-25

申请号：US18545419

申请日：2023-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin PARK ,  Kyujin KIM ,  Chulkwon PARK ,  Sunghee HAN

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: A semiconductor memory device includes a substrate comprising a memory cell region and a dummy cell region surrounding the memory cell region, the memory cell region including a plurality of memory cells, a plurality of active regions in the memory cell region, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction with respect to a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of active regions having a first width in a short axis direction orthogonal to the long axis direction, and a plurality of dummy active regions in the dummy cell region, each extending in the long axis direction, each of the plurality of dummy active regions having a second width greater than the first width in the short axis direction.

公开(公告)号：US20240032280A1

公开(公告)日：2024-01-25

申请号：US18224802

申请日：2023-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejin PARK ,  Kyujin KIM ,  Bongsoo KIM ,  Huijung KIM ,  Chulkwon PARK ,  Gyunghyun YOON ,  Heejae CHAE

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053

Abstract: An Integrated Circuit (IC) semiconductor device includes: field insulating layers buried in field trenches disposed apart from each other inside a substrate; active regions defined by the field insulating layers; and active fins disposed on the active regions and protruding from surfaces of the field insulating layers. The field insulating layers include a first subfield insulating layer and a second subfield insulating layer, and a surface of the first subfield insulating layer is disposed at a level lower than a level of a surface of the second subfield insulating layer.

公开(公告)号：US20240029667A1

公开(公告)日：2024-01-25

申请号：US18474722

申请日：2023-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongheon SHIN ,  Taejin PARK ,  Donghwy KIM ,  Jiyong KIM ,  Heekeun PARK ,  Minwoo LEE ,  Hoondo HEO ,  Minho KIM ,  Hyojong KIM

IPC: G09G3/34

CPC classification number: G09G3/3406 ,  G09G2320/0626 ,  G09G2360/142 ,  G09G2354/00

Abstract: An electronic device configured to configure brightness of a display by using an illuminance sensor is provided. The electronic device includes acquiring a second front-surface sensing value smaller than a first front-surface sensing value through a first illuminance sensor while the brightness is a first brightness, comparing the second front-surface sensing value with a first rear-surface sensing value detected through a second illuminance sensor, determining, when the second front-surface sensing value is greater than the first rear-surface sensing value, whether a touch input is detected through a designated region of the display, maintaining the brightness at the first brightness when the touch input is detected, and when the touch input is not detected, adjusting the brightness of the display to a value lower than that of the first brightness, based on a first LUT stored in a memory, or maintaining the brightness of the display at the first brightness.

公开(公告)号：US20230024913A1

公开(公告)日：2023-01-26

申请号：US17949418

申请日：2022-09-21

Applicant: Samsung Electronics Co., Ltd. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Kyung-Eun BYUN ,  Hyoungsub KIM ,  Taejin PARK ,  Hoijoon KIM ,  Hyeonjin SHIN ,  Wonsik AHN ,  Mirine LEEM ,  Yeonchoo CHO

IPC: H01L21/02

Abstract: A method of forming a transition metal dichalcogenide thin film on a substrate includes treating the substrate with a metal organic material and providing a transition metal precursor and a chalcogen precursor around the substrate to synthesize transition metal dichalcogenide on the substrate. The transition metal precursor may include a transition metal element and the chalcogen precursor may include a chalcogen element.

公开(公告)号：US20220223115A1

公开(公告)日：2022-07-14

申请号：US17577545

申请日：2022-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minho KIM ,  Gilyoung NOH ,  Taejin PARK ,  Dongin KIM ,  Hyosun KIM ,  Jaehun LIM ,  Hyojong KIM

IPC: G09G3/34

Abstract: An electronic device according to an embodiment may include a display, a touch sensor, an illuminance sensor configured to generate illuminance information, a memory configured to store brightness data relating the ambient illuminance to brightness of the display, and a processor. The processor may be configured to identify the illuminance information from the illuminance sensor, configure the brightness of the display as first brightness, based on the illuminance information and the brightness data, change the brightness of the display to second brightness, based on a user input, acquire event information for an operation in which the brightness of the display is changed by the user input, reconfigure the brightness data stored in the memory, based on the event information, and determine the brightness of the display according to a brightness value mapped in the reconfigured brightness data to the illuminance information identified by the illuminance sensor.

公开(公告)号：US20240315005A1

公开(公告)日：2024-09-19

申请号：US18388266

申请日：2023-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Sangjae PARK ,  Huijung KIM ,  Taejin PARK ,  Chansic YOON ,  Myeongdong LEE

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/482

Abstract: A semiconductor device includes an active pattern array including active patterns on a substrate; a first contact structure on a central portion of each active pattern; a bit line structure on the first contact structure; a second contact structure on an end of each active pattern; a third contact structure on the second contact structure; and a capacitor electrically connected to the third contact structure, wherein the active pattern array includes active pattern rows spaced apart from each other in a second direction parallel the substrate, the active pattern rows include active patterns spaced apart from each other in a first direction parallel to the substrate, the active patterns extend in a third direction having an acute angle with the first/second directions, the active patterns in the rows are aligned in the first direction, and the second contact structure has a rectangular shape in a plan view.

公开(公告)号：US20240284662A1

公开(公告)日：2024-08-22

申请号：US18435231

申请日：2024-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heejae CHAE ,  Taejin PARK ,  Hyunjin LEE ,  Hosang LEE ,  Yun CHOI

IPC: H10B12/00 ,  H01L21/762 ,  H01L29/49

CPC classification number: H10B12/488 ,  H01L21/76232 ,  H01L29/4916 ,  H10B12/34

Abstract: A semiconductor device includes a substrate including a word line trench extending in a first horizontal direction; a gate dielectric layer in the word line trench; a word line extending in the first horizontal direction and in a lower portion of the word line trench on the gate dielectric layer; an insulation capping layer extending in an upper portion of the word line trench on the word line; and a plurality of gate electrodes on the substrate, wherein the word line comprises: a word line lower region extending in the first horizontal direction and including a first gate electrode of the plurality of gate electrodes on the gate dielectric layer; and a word line upper region extending in the first horizontal direction on the word line lower region and including a plurality of second gate electrodes of the plurality of gate electrodes and the first gate electrode.

公开(公告)号：US20240268102A1

公开(公告)日：2024-08-08

申请号：US18471583

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Seung-Bo KO ,  Jongmin KIM ,  Hui-Jung KIM ,  SangJae PARK ,  Taejin PARK ,  Chan-Sic YOON ,  Myeong-Dong LEE ,  Hongjun LEE ,  Minju KANG ,  Keunnam KIM

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor device includes first and second active patterns extending in a first direction and arranged in a second direction intersecting the first direction, each of the first and second active patterns including first and second edge portions spaced apart from each other in the first direction, a first storage node pad and a first storage node contact sequentially provided on the first edge portion of the first active pattern, and a second storage node pad and a second storage node contact sequentially provided on the second edge portion of the second active pattern. Each of the first and second storage node contacts includes a metal material.

公开(公告)号：US20240130112A1

公开(公告)日：2024-04-18

申请号：US18464475

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin PARK ,  Bongsoo KIM ,  Huijung KIM

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/485 ,  H10B12/488

Abstract: Provided is an integrated circuit device including a substrate that has an active region defined by a plurality of device separation regions, a word line on the substrate and arranged in a word line trench that extends in a first horizontal direction, a bit line on the word line and extending in a second horizontal direction orthogonal to the first horizontal direction, a pad on the active region and having a horizontal width that is larger than the active region, and a bit line contact electrically connecting the bit line to the active region, wherein a level of a lowermost surface of the additional pad is at a same vertical level as a level of a lowermost surface of the bit line contact.

公开(公告)号：US20230044856A1

公开(公告)日：2023-02-09

申请号：US17873242

申请日：2022-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejin PARK ,  Kiseok LEE ,  Hui-Jung KIM ,  Yoosang HWANG

IPC: H01L29/423 ,  H01L21/768 ,  H01L21/762 ,  H01L21/02 ,  G11C5/06

Abstract: A semiconductor memory device including a substrate including an active pattern that includes a first source/drain region and a second source/drain region; an insulating layer on the substrate; a line structure on the insulating layer and extending in a first direction to cross the active pattern, the line structure penetrating the insulating layer on the first source/drain region and including a bit line electrically connected to the first source/drain region; and a contact spaced apart from the line structure and electrically connected to the second source/drain region, wherein the bit line includes a first portion vertically overlapped with the first source/drain region; and a second portion vertically overlapped with the insulating layer, and wherein a lowermost level of a top surface of the first portion of the bit line is at a level lower than a lowermost level of a top surface of the second portion of the bit line.