Memory device using a plurality of supply voltages and operating method thereof

    公开(公告)号:US11990179B2

    公开(公告)日:2024-05-21

    申请号:US17478629

    申请日:2021-09-17

    CPC classification number: G11C11/419 G11C11/418

    Abstract: A memory device accessed by circuits operating based on a first supply voltage. The memory device includes a cell array electrically connected to a plurality of word lines and a plurality of bit lines; a row driver configured to select one word line of the plurality of word lines based on a row address; a precharge circuit configured to precharge the plurality of bit lines based on the first supply voltage; a column driver configured to select at least one bit line of the plurality of bit lines based on a column address; and a read circuit configured to read data stored in the cell array through the at least one bit line. The cell array, the row driver, the column driver, and the read circuit operate based on a second supply voltage, which is higher than the first supply voltage.

    DESICCANT REPLACING APPARATUS AND AIR DRY SYSTEM INCLUDING THE SAME

    公开(公告)号:US20220111331A1

    公开(公告)日:2022-04-14

    申请号:US17306352

    申请日:2021-05-03

    Abstract: A desiccant replacing apparatus may include a supply-discharge member, a supply connection line connected to the supply-discharge member, an air conveyor coupled to the supply connection line, a discharge connection line connected to the supply-discharge member, and an air amplifier coupled to the discharge connection line. The supply-discharge member may include a housing providing an internal space, an injection line providing an injection path and penetrating the housing, an exhaust line providing an exhaust path connected to the internal space, and a filter in the internal space or the exhaust path. The supply connection line may be connected to the injection line, and the discharge connection line may be connected to the exhaust line.

    Storage device and operating method thereof

    公开(公告)号:US11112997B2

    公开(公告)日:2021-09-07

    申请号:US16394506

    申请日:2019-04-25

    Abstract: An operating method of a storage device which includes a first nonvolatile memory device and a second nonvolatile memory device includes detecting sudden power-off, suspending an operation being performed in the first nonvolatile memory device, in response to the detected sudden power-off, writing suspension information about the suspended operation into the second nonvolatile memory device, and performing a block management operation on the first nonvolatile memory device based on the suspension information written into the second nonvolatile memory device, in power-up after the sudden power-off.

    HIGH VOLTAGE SWITCH AND A NONVOLATILE MEMORY DEVICE INCLUDING THE SAME
    17.
    发明申请
    HIGH VOLTAGE SWITCH AND A NONVOLATILE MEMORY DEVICE INCLUDING THE SAME 有权
    高电压开关和非易失性存储器件,包括它们

    公开(公告)号:US20140204676A1

    公开(公告)日:2014-07-24

    申请号:US14077769

    申请日:2013-11-12

    CPC classification number: G11C16/30 G11C16/0483 G11C16/12

    Abstract: A high voltage switch of a nonvolatile memory device includes a depletion type NMOS transistor configured to switch a second driving voltage in response to an output signal of the high voltage switch; at least one inverter configured to convert a voltage of an input signal of the high voltage switch into a first driving voltage or a ground voltage, wherein the first and second driving voltages are received from an external device; and a PMOS transistor configured to transfer the second driving voltage provided to a first terminal of the PMOS transistor from the depletion type NMOS transistor to a second terminal of the PMOS transistor as the output signal in response to an output of the at least one inverter, wherein the output of the at least one inverter is transferred to a gate terminal of the PMOS transistor.

    Abstract translation: 非易失性存储器件的高电压开关包括耗尽型NMOS晶体管,其配置为响应于高电压开关的输出信号而切换第二驱动电压; 至少一个反相器,被配置为将高压开关的输入信号的电压转换为第一驱动电压或接地电压,其中从外部装置接收第一和第二驱动电压; 以及PMOS晶体管,被配置为响应于所述至少一个反相器的输出,将提供给所述PMOS晶体管的第一端子的所述第二驱动电压从所述耗尽型NMOS晶体管传送到所述PMOS晶体管的第二端子作为所述输出信号, 其中所述至少一个反相器的输出被传送到所述PMOS晶体管的栅极端子。

    MEMORY DEVICE USING A PLURALITY OF SUPPLY VOLTAGES AND OPERATING METHOD THEREOF

    公开(公告)号:US20240282367A1

    公开(公告)日:2024-08-22

    申请号:US18639330

    申请日:2024-04-18

    CPC classification number: G11C11/419 G11C11/418

    Abstract: A memory device accessed by circuits operating based on a first supply voltage. The memory device includes a cell array electrically connected to a plurality of word lines and a plurality of bit lines; a row driver configured to select one word line of the plurality of word lines based on a row address; a precharge circuit configured to precharge the plurality of bit lines based on the first supply voltage; a column driver configured to select at least one bit line of the plurality of bit lines based on a column address; and a read circuit configured to read data stored in the cell array through the at least one bit line. The cell array, the row driver, the column driver, and the read circuit operate based on a second supply voltage, which is higher than the first supply voltage.

    SIMULATION METHOD AND SIMULATION DEVICE
    19.
    发明公开

    公开(公告)号:US20240143876A1

    公开(公告)日:2024-05-02

    申请号:US18462702

    申请日:2023-09-07

    CPC classification number: G06F30/27 G06N3/092 H03K19/20

    Abstract: A simulation method and a simulation device are disclosed. A simulation method according to the inventive concept is provided. A simulation method of the inventive concept may include obtaining an initial state variable and an initial reward variable detected from the semiconductor device, training an agent to output a first action variable of a reinforcement learning model based on the initial state variable and the initial reward variable; and generating a first state variable of the reinforcement learning model and generating a first reward variable, based on the first action variable, wherein the first reward variable includes a skew reward variable for rewarding a skew occurring in the semiconductor device and a duty reward variable for rewarding a duty error rate of an output signal output from the semiconductor device.

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