公开(公告)号：US20230345696A1

公开(公告)日：2023-10-26

申请号：US18132198

申请日：2023-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokhan Park ,  Bowon Yoo ,  Hyunseo Shin ,  Kiseok Lee ,  Moonyoung Jeong

IPC: H10B12/00

CPC classification number: H10B12/0387 ,  H10B12/0383 ,  H10B12/488

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of first trenches in a substrate. A plurality of first filling layers is formed that fills the first trenches and have protrusions extending to protrude from the substrate. Spacers are formed on sidewalls of the protrusions of the first filling layers. The spacers expose portions of the substrate between adjacent first filling layers. A plurality of second trenches is formed around the first trenches by etching the portions of the substrate exposed by the spacers. A plurality of second filling layers is formed that fills the second trenches. All of the first filling layers and the spacers are removed. A gate material layer is formed that conformally covers inner walls of the first trenches. A pair of gate structures is formed in each of the first trenches by separating the gate material layer.

公开(公告)号：US10910378B2

公开(公告)日：2021-02-02

申请号：US16268748

申请日：2019-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Bong-Soo Kim ,  Jiyoung Kim ,  Hui-Jung Kim ,  Seokhan Park ,  Hunkook Lee ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/08 ,  H01L29/165 ,  H01L29/10 ,  H01L23/522 ,  H01L49/02

Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

公开(公告)号：US20200092506A1

公开(公告)日：2020-03-19

申请号：US16394541

申请日：2019-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhan Park ,  Jaekyu Lee ,  Kijae Hur

IPC: H04N5/369 ,  H01L27/146 ,  H01L23/528 ,  G11C11/408 ,  H01L27/108 ,  H01L23/48 ,  G11C11/4074 ,  H01L25/18 ,  H04N5/378

Abstract: An image sensor in which a pixel array and a memory cell array are merged includes a first semiconductor chip including the pixel array and the memory cell array in a same semiconductor chip, and a second semiconductor chip overlapping the first semiconductor chip in a vertical direction. The second semiconductor chip includes a first logic circuit that controls the pixel array, an analog-to-digital converter (ADC) that converts an analog signal output from the pixel array under control of the first logic circuit to a digital signal, and a second logic circuit that stores data that is output from the ADC circuit based on the digital signal to the memory cell array of the first semiconductor chip.

公开(公告)号：US10461153B2

公开(公告)日：2019-10-29

申请号：US15890707

申请日：2018-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Myeong-Dong Lee ,  Hui-Jung Kim ,  Dongoh Kim ,  Bong-Soo Kim ,  Seokhan Park ,  Woosong Ahn ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L29/06 ,  H01L27/108 ,  H01L23/535 ,  H01L23/528

Abstract: A semiconductor memory device includes a substrate including active regions, word lines in the substrate and each extending in a first direction parallel to an upper surface of the substrate, bit line structures connected to the active regions, respectively, and each extending in a second direction crossing the first direction, and spacer structures on sidewalls of respective ones of the bit line structures. Each of the spacer structures includes a first spacer, a second spacer, and a third spacer. The second spacer is disposed between the first spacer and the third spacer and includes a void defined by an inner surface of the second spacer. A height of the second spacer is greater than a height of the void.

公开(公告)号：US20240389308A1

公开(公告)日：2024-11-21

申请号：US18589891

申请日：2024-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjun Lee ,  Seokhan Park ,  Iljae Shin ,  Kiseok Lee ,  Sanghyun Lee

IPC: H10B12/00 ,  H01L23/528 ,  H01L29/08 ,  H01L29/417

Abstract: A semiconductor device includes a substrate including a memory cell array region, a contact region, and a connection region, gate electrodes on the memory cell array region and the connection region, and stacked in a vertical direction, active layers on the memory cell array region and stacked in the vertical direction, and conductive connection patterns on the connection region and the contact region, and stacked in the vertical direction, wherein each of the active layers includes a channel region vertically overlapping the gate electrodes, the gate electrodes are electrically connected to the conductive connection patterns, the conductive connection patterns have a step structure including step regions spaced apart from each other, and the step structure has a first step portion stepping down along a first direction and a second step portion facing the first step portion and stepping up along the first direction.

公开(公告)号：US11996457B2

公开(公告)日：2024-05-28

申请号：US17443553

申请日：2021-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Ilgweon Kim ,  Seokhan Park ,  Kyunghwan Lee ,  Jaeho Hong

IPC: H01L29/423 ,  H01L23/482 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L23/4828 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first conductive pattern, a gate insulation pattern, a second conductive pattern and a second impurity region. Each of the semiconductor structures includes a first semiconductor pattern that has a linear shape that extends in a first direction and second semiconductor patterns that protrude from an upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion harrier pattern and a polysilicon pattern doped with impurities.

公开(公告)号：US20240170574A1

公开(公告)日：2024-05-23

申请号：US18518264

申请日：2023-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongchan Shin ,  Kiseok Lee ,  Seokhan Park ,  Seokho Shin

IPC: H01L29/78 ,  H10B12/00

CPC classification number: H01L29/7827 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/50

Abstract: A semiconductor device includes a vertical channel transistor including a vertical channel region extending in a vertical direction and a cell gate electrode facing a first side surface of the vertical channel region. A bit line is electrically connected to the vertical channel transistor at a level that is lower than a level of the vertical channel transistor. A peripheral semiconductor body has at least a portion thereof disposed on a same level as the vertical channel region. Peripheral source/drain regions are disposed in the peripheral semiconductor body and are spaced apart from each other in a horizontal direction. A peripheral channel region is disposed between the peripheral source/drain regions in the peripheral semiconductor body. A peripheral gate is disposed below the peripheral semiconductor body. At least a portion of the peripheral gate is disposed on a same level as at least a portion of the bit line.

公开(公告)号：US11765880B2

公开(公告)日：2023-09-19

申请号：US17245912

申请日：2021-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanghee Lee ,  Seokhan Park ,  Sungchang Park ,  Boun Yoon ,  Ilyoung Yoon ,  Youngsuk Lee ,  Junseop Lee ,  Seungho Han ,  Jaeyong Han ,  Jeehwan Heo

IPC: H10B12/00

CPC classification number: H10B12/01

Abstract: A method of manufacturing a semiconductor device includes: forming a lower structure that includes a substrate and conductive lines on the substrate, within a chip region and an edge region of the lower structure; forming data storage structures on the chip region of the lower structure; forming dummy structures on the edge region of the lower structure; forming an interlayer insulating layer covering the data storage structures and the dummy structures on the lower structure, the interlayer insulating layer including high step portions and low step portions, an upper end of the low step portions being lower than an upper end of the high step portions; and planarizing the interlayer insulating layer.

公开(公告)号：US11342436B2

公开(公告)日：2022-05-24

申请号：US16801508

申请日：2020-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Hong ,  Yongseok Kim ,  Hyuncheol Kim ,  Seokhan Park ,  Satoru Yamada ,  Kyunghwan Lee

IPC: H01L29/51 ,  H01L29/423 ,  H01L27/108 ,  H01L29/08

Abstract: A semiconductor device includes a substrate including a recess, a first gate insulation layer on a lower sidewall and a bottom of the recess, the first gate insulation layer including an insulation material having hysteresis characteristics, a first gate electrode on the first gate insulation layer inside the recess, a second gate electrode contacting the first gate electrode in the recess, the second gate electrode including a material different from a material of the first gate electrode, and impurity regions on the substrate and adjacent to sidewalls of the recess, bottoms of the impurity regions being higher than a bottom of the second gate electrode relative to a bottom of the substrate.

公开(公告)号：US20220115379A1

公开(公告)日：2022-04-14

申请号：US17245912

申请日：2021-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanghee Lee ,  Seokhan Park ,  Sungchang Park ,  Boun Yoon ,  Ilyoung Yoon ,  Youngsuk Lee ,  Junseop Lee ,  Seungho Han ,  Jaeyong Han ,  Jeehwan Heo

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor device includes: forming a lower structure that includes a substrate and conductive lines on the substrate, within a chip region and an edge region of the lower structure; forming data storage structures on the chip region of the lower structure; forming dummy structures on the edge region of the lower structure; forming an interlayer insulating layer covering the data storage structures and the dummy structures on the lower structure, the interlayer insulating layer including high step portions and low step portions, an upper end of the low step portions being lower than an upper end of the high step portions; and planarizing the interlayer insulating layer.