公开(公告)号：US20220058331A1

公开(公告)日：2022-02-24

申请号：US17360355

申请日：2021-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungman LIM ,  Hakchul JUNG ,  Sanghoon BAEK ,  Jaewoo SEO ,  Jisu YU ,  Hyeongyu YOU

IPC: G06F30/3953 ,  H01L23/528

Abstract: An integrated circuit includes a plurality of logic cells arranged in a first row extending in a first direction and including different types of active areas extending in the first direction, a filler cell arranged in a second row adjacent to the first row in a second direction orthogonal to the first direction and extending in the first direction, and a first routing wiring line arranged in the second row and connecting a first logic cell and a second logic cell apart from each other by a first distance among the plurality of logic cells. A height of the first row is different from a height of the second row.

公开(公告)号：US20210175170A1

公开(公告)日：2021-06-10

申请号：US16910748

申请日：2020-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon BAEK ,  Seung Young LEE

IPC: H01L23/528

Abstract: A semiconductor device is provided. The semiconductor device includes a first-direction plurality of wirings extending in a first direction, and a second-direction plurality of wiring extending in a second direction intersecting the first direction. The first-direction plurality of wirings that extend in the first direction includes gate wirings spaced apart from each other in the second direction by a gate pitch, first wirings above the gate wirings spaced apart from each other in the second direction by a first pitch, second wirings above the first wirings spaced apart from each other in the second direction by a second pitch, and third wirings above the second wirings spaced apart from each other in the second direction by a third pitch. A ratio between the gate pitch and the second pitch is 6:5.

公开(公告)号：US20170365593A1

公开(公告)日：2017-12-21

申请号：US15692670

申请日：2017-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyoung LEE ,  Sanghoon BAEK ,  Jung-Ho DO

IPC: H01L27/02 ,  H01L23/528 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/66628 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, an insulating layer on the gate electrode, first and second lower vias in the insulating layer, first and second lower metal lines provided on the insulating layer and respectively connected to the first and second lower vias, and first and second upper metal lines provided on and respectively connected to the first and second lower metal lines. When viewed in a plan view, the first lower via is overlapped with the second upper metal line, and the second lower via is overlapped with the first upper metal line.

公开(公告)号：US20240332305A1

公开(公告)日：2024-10-03

申请号：US18743961

申请日：2024-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon BAEK ,  Jungho DO ,  Jaewoo SEO ,  Jisu YU

IPC: H01L27/118 ,  H01L23/48 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L23/481 ,  H01L27/0207 ,  H01L2027/11829 ,  H01L2027/11864 ,  H01L2027/11881

Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

公开(公告)号：US20230335559A1

公开(公告)日：2023-10-19

申请号：US18336754

申请日：2023-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon BAEK ,  Jungho DO ,  Jaewoo SEO ,  Jisu YU

IPC: H01L27/118 ,  H01L27/02 ,  H01L23/48

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L23/481 ,  H01L2027/11864 ,  H01L2027/11881 ,  H01L2027/11829

Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

公开(公告)号：US20220300693A1

公开(公告)日：2022-09-22

申请号：US17669631

申请日：2022-02-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungho DO ,  Jaewoo SEO ,  Sanghoon BAEK ,  Jisu YU ,  Hyeongyu YOU ,  Minjae JEONG

IPC: G06F30/394 ,  G06F30/392

Abstract: An integrated circuit includes a first cell including a first lower pattern extending in a first direction along a first track in a first wiring layer; and a second cell including a second lower pattern that extends in the first direction along the first track in the first wiring layer, and is a minimum space of the first wiring layer or farther apart from the first lower pattern, wherein the first lower pattern corresponds to a pin of the first cell, and the second lower pattern is farther apart from a boundary between the first cell and the second cell than the first lower pattern is.

公开(公告)号：US20220270969A1

公开(公告)日：2022-08-25

申请号：US17740453

申请日：2022-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon BAEK ,  Seung Young LEE

IPC: H01L23/528

Abstract: A semiconductor device is provided. The semiconductor device includes a first-direction plurality of wirings extending in a first direction, and a second-direction plurality of wiring extending in a second direction intersecting the first direction. The first-direction plurality of wirings that extend in the first direction includes gate wirings spaced apart from each other in the second direction by a gate pitch, first wirings above the gate wirings spaced apart from each other in the second direction by a first pitch, second wirings above the first wirings spaced apart from each other in the second direction by a second pitch, and third wirings above the second wirings spaced apart from each other in the second direction by a third pitch. A ratio between the gate pitch and the second pitch is 6:5.

公开(公告)号：US20210328056A1

公开(公告)日：2021-10-21

申请号：US17138027

申请日：2020-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon BAEK ,  Jeong Soon Kong ,  Jung Ho Do

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/417

Abstract: Provided is an integrated circuit implemented by a plurality of vertical field effect transistors (VFETs) in one or more semiconductor cells, wherein a distance between a pair of second vertical channel structures of a first cell and an adjacent pair of first vertical channel structures in a second cell, all facing a cell boundary between the first and second cells, is the same as a distance between the pair of the first vertical channel structures and a pair of second vertical channel structures arranged next to the pair of the first vertical channel structures in the first cell.

公开(公告)号：US20210167090A1

公开(公告)日：2021-06-03

申请号：US17027211

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Su YU ,  Jae-Ho PARK ,  Sanghoon BAEK ,  Hyeon Gyu YOU ,  Seung Young LEE ,  Seung Man LIM

IPC: H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a first standard cell including a first p-type transistor, a first n-type transistor, a first gate stack intersecting first and second active regions, first extended source/drain contacts on a first side of the first gate stack, a first normal source/drain contact on a second side of the first gate stack, a first gate via connected to the first gate stack, and a first source/drain via connected to the first normal source/drain contact, a second standard cell adjacent the first standard cell and including a second p-type transistor, a second n-type transistor, a second gate stack intersecting the first and second active regions, and a second gate via connected to the second gate stack, an input wiring connected to the first gate via, and an output wiring at a same level as the input wiring to connect the first source/drain via and the second gate via.

公开(公告)号：US20200212069A1

公开(公告)日：2020-07-02

申请号：US16817094

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong SONG ,  Ha-Young KIM ,  Jung-Ho DO ,  Sanghoon BAEK ,  Jinyoung LIM ,  Kwangok JEONG

IPC: H01L27/118 ,  H01L27/092 ,  H01L27/02 ,  H01L21/66 ,  H01L21/8238 ,  H01L49/02 ,  H01L27/11582 ,  G03F1/36 ,  G06F30/398 ,  G06F30/394 ,  G06F30/327 ,  G06F30/30

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.