公开(公告)号：US20220246601A1

公开(公告)日：2022-08-04

申请号：US17720153

申请日：2022-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon BAEK ,  Myung Gil KANG ,  Jae-Ho PARK ,  Seung Young LEE

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L27/118

Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.

公开(公告)号：US20210074697A1

公开(公告)日：2021-03-11

申请号：US16842053

申请日：2020-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon BAEK ,  Myung Gil KANG ,  Jae-Ho PARK ,  Seung Young LEE

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.

公开(公告)号：US20200243523A1

公开(公告)日：2020-07-30

申请号：US16531327

申请日：2019-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Boong LEE ,  Jae-Ho PARK ,  Sang-Hoon BAEK ,  Ji-Su YU ,  Seung-Young LEE ,  Jong-Hoon JUNG

IPC: H01L27/092 ,  H01L29/06

Abstract: A semiconductor device includes first group active fins and a first diffusion prevention pattern. The first group active fins are spaced apart from each other in a second direction, and each of the first group active fins extends in a first direction different from the second direction on a first region of a substrate including the first region and a second region. The first diffusion prevention pattern extends on the first region of the substrate in the second direction through the first group active fins. The first group active fins include first and second active fins. The first diffusion prevention pattern extends through a central portion of the first active fin in the first direction to divide the first active fin, and extends through and contacts an end of the second active fin in the first direction.

公开(公告)号：US20210167090A1

公开(公告)日：2021-06-03

申请号：US17027211

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Su YU ,  Jae-Ho PARK ,  Sanghoon BAEK ,  Hyeon Gyu YOU ,  Seung Young LEE ,  Seung Man LIM

IPC: H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a first standard cell including a first p-type transistor, a first n-type transistor, a first gate stack intersecting first and second active regions, first extended source/drain contacts on a first side of the first gate stack, a first normal source/drain contact on a second side of the first gate stack, a first gate via connected to the first gate stack, and a first source/drain via connected to the first normal source/drain contact, a second standard cell adjacent the first standard cell and including a second p-type transistor, a second n-type transistor, a second gate stack intersecting the first and second active regions, and a second gate via connected to the second gate stack, an input wiring connected to the first gate via, and an output wiring at a same level as the input wiring to connect the first source/drain via and the second gate via.